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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 5/2021

06.08.2021

The design, analysis, and simulation of an optimized all-optical AND gate using a Y-shaped plasmonic waveguide for high-speed computing devices

verfasst von: Surya Pavan Kumar Anguluri, Srinivas Raja Banda, Sabbi Vamshi Krishna, Sandip Swarnakar, Santosh Kumar

Erschienen in: Journal of Computational Electronics | Ausgabe 5/2021

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Abstract

All-optical logic gates have proven their significance in the digital world for the implementation of high-speed computations. We propose herein a novel structure for an all-optical AND gate using the concept of a power combiner based on a Y-shaped metal–insulator–metal waveguide with a 4 µm × 7 µm footprint. This design works based on the principle of linear interference. The insertion loss and extinction ratio of the design are given as 0.165 and 14.11 dB, respectively. The design is analyzed by using the finite-difference time-domain (FDTD) method and verified using MATLAB. The minimized structure can be used to design any complex logic circuit to achieve better performance in the future.
Vorheriger Artikel Correction to: Analysis of all-optical priority encoder using plasmonics waveguide
Nächster Artikel Analysis and design of a passive spatial filter for sub-6 GHz 5G communication systems

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Metadaten
Titel
The design, analysis, and simulation of an optimized all-optical AND gate using a Y-shaped plasmonic waveguide for high-speed computing devices
verfasst von
Surya Pavan Kumar Anguluri
Srinivas Raja Banda
Sabbi Vamshi Krishna
Sandip Swarnakar
Santosh Kumar
Publikationsdatum
06.08.2021
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 5/2021
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-021-01748-x

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