Novel high multilevel inverters investigated on simulation

This paper presents a novel high multilevel inverter topology which is based on the created DC voltage levels at loads of the inverter. The circuit model is demonstrated by explaining the relationship between switches, sources and loads. According to the proposed inverter topology, the number of power switches connected to negative side of DC source is constant on inverter, while the number of power switches connected to positive side of DC sources is increasing. Therefore, linear pulse-width modulation (LPWM) is described for operating switches after pulse-width modulation method is developed to generate the PWM signals. Then, mathematical equations are given when resistive (R), inductive (L) and capacitive (C) loads are connected in series on a 9-level inverter. Finally, the performances of the proposed inverters are observed through MATLAB/SIMULINK simulations after the designed multilevel inverters are simulated. So, 6-level, 9-level and 11-level inverters are compared with voltages, currents and harmonic distortions. Harmonic distortions reduce with increasing level of inverter, while three multilevel inverters are investigated on different modulation indexes. The results demonstrate the satisfactory performance of the inverter and verify the effectiveness of a novel high multilevel inverter topology.