High-κ dielectrics and advanced channel concepts for Si MOSFET

With scaling of the gate length downward to increase speed and density, the gate dielectric thickness must also be reduced. However, this practice which has been in effect for many decades has reached a fundamental limitation because gate dielectric thicknesses in the range of tunneling have been reached with the SiO₂ dielectric layer for MOSFETs. Consequently, the gate dielectrics with higher dielectric constants, dubbed the “high-κ”, which allow scaling with much larger thicknesses have become active research and development topics. In this review technological issues associated with the likely high-κ materials which are under consideration as well as challenges, and solution to them, they bring about in the fabrication of Si MOSFET are discussed. Moreover, in order to squeeze more speed out of CMOS, channels for both n- and p-type MOSFET enhanced with appropriate strain and the concepts behind them are discussed succinctly. Finally, the longer term approach of replacing Si with other channel materials such as GaAs (InGaAs) for n-channel and Ge for p-channel along with technological developments of their preparation on Si and likely gate oxide developments are treated in some detail.