Materials & Process Integration for MEMS

This chapter presents an overview on integration processes that have been developed for the fabrication of planar silicon structures coated by textured piezoelectric Pb(Zr_xTi_1−x)O₃ (PZT) thin films. Key issues are the textured growth to achieve high piezoelectric coefficients and the stress compensation to control the bending of cantilevers as well as the stretching forces at membranes. Advanced dry etching techniques are needed for patterning the electrode films without damage to PZT, and without leaving residues. Some recent results on cantilever-microphone and piezoelectric micromachined ultrasonic transducer (pMUT) are presented.

This chapter discusses the use of porous silicon as a sacrificial supporting layer during silicon diaphragm formation by precision grinding. Unsupported silicon diaphragms formed by grinding exhibit post-grinding shape distortion dependent upon diaphragm thickness and diameter. Such distortion can be eliminated or strongly suppressed by use of a support during the grinding process. Use of porous silicon as in-situ support for 15 – 150 μm thick diaphragms is explained with emphasis on porous silicon properties, diaphragm thickness and fabrication processing steps such as oxidation.

Silicon (Si) based MicroElectroMechanical Systems (MEMS) are now a well understood and widely used in various integrated micromachined microsensors and microactuators. In relation to this, Gallium Arsenide (GaAs) offers a number of material-related and technological advantages over Si. This paper is an attempt to demonstrate a high potential of GaAs based heterostructures for the development of a new generation of MEMS devices. There are 1 μtm-thick cantilever and bridge membrane-like structures fully compatible with both AlGaAs/InGaAs/GaAs and InGaP/InGaAs/GaAs based HFETs developed. The basic electro-thermo-mechanical properties of the micromechanical structures are investigated. A high electro-thermal conversion efficiency is studied in various ambient atmospheres. An internal mechanical stress induced in the micromechanical structures is evaluated to be admissible for their mechanical integrity and stability. This makes the structures very attractive for the design of new thermally based MEMS devices.

TiNiCu films were successfully prepared by co-sputtering of a TiNi target and a separate Cu target. Surface and cross-section microstructures of the deposited coating were analysed using Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and Transmission Electron Microscopy (TEM). Results showed that the deposited coating had fine grain size of about 300 to 400 nm and fully martensitic structure under room temperature. X-Ray Photoelectron Spectroscopy (XPS) indicated that there was an adherent and stable TiO₂ oxide film on TiNiCu film surface, which can prevent Ni element from delamination. The deposited TiNiCu film has relatively strong (11 1) and (111) and relatively weak (010) texture. Results from Differential Scanning Calorimeter (DSC), in-situ X-Ray Diffraction (XRD) and curvature measurement revealed clearly martensitic transformation of the deposited TiNiCu films upon heating and cooling. Freestanding TiNiCu thin film showed clearly pronounced “two-way” shape memory effect, which is quite applicable to develop thin film micro-actuators. By depositing TiNi films on the bulk micromachined Si cantilever structures, micro-beams exhibiting good shape-memory effect were obtained. This type of cantilever structure can be further fabricated as a micro-gripper which can be used as the end-manipulator for micro-assembly in industry, minimally invasive surgery for medical application, and handling of small particles in hazardous environment for military application.

New-generation Chemically Amplified Resists (CARs) such as the positive tone commercial UVIII resist offer a substantial gain in sensitivity, resolution, and process efficiency in deep ultraviolet, electron-beam, and x-ray lithographies. These characteristics are useful for the fabrication of structures for MEMS applications. In this work, the UVIII resist is characterised for x-ray lithographic applications by studying the “deprotection” or acid generation-diffusion process of the resist under different conditions of poste-xposure bake temperature and time, and of x-ray exposure time or dose. The x-ray irradiation from an aluminium anode at the wavelength of 0.83 nm was at an intensity of 45 μW/cm² on the resist surface. The deprotection process of the resist during post-exposure bake was monitored by using Fourier Transform Infrared (FTIR) spectroscopy. Results showed that the performance of UVIII could be optimised at the post-bake temperature of 140^oC and time of 2 minutes, and x-ray exposure dose of 18 mJ/cm². The results were confirmed by Scanning Electron Microscopic (SEM) studies on UVIII test structures, which were processed using the optimised condition. Test structure as small as 150 nm was obtained in 7 μm thick UVIII resist layer.

In this research, we explore the use of SAM (Self-Assembled Monolayers) materials for improving the robustness of a tunneling accelerometer. For gold coated tip-gold sample, the results are comparable with expectations for tunneling between gold electrodes in air. Using SAM materials, the robustness of the tunnel tips in terms of reliability shows promise of improved characteristics.

In this paper, the principle, device structure and the fabrication of bulk micro machined accelerometer are presented. It has been observed that the same oxidation process which resulted in low leakage current for small area devices gave rise to high leakage current in the large area Silicon Fusion Bonded structures. Using large area MOS devices as the test vehicle, it is shown that such high leakage current problems can be sorted out by carrying out oxidation by a two-step dry-wet oxidation process at 1000⁰C. It is also shown that the two-step oxidation process leads to MOS capacitors with leakage currents considerably smaller than the devices fabricated with totally dry oxidation or totally wet oxidation process.

Nanofabrication and fabrication of nanodevices on single-crystal silicon have been demonstrated by electric-field-enhanced local oxidation on semiconductor materials using a Scanning Probe Microscope (SPM). The advantages of the SPM lithography technique are its high resolution and absence of radiation damage in the substrate to be patterned. Scanning Probe Lithography (SPL) is highly dependent on tip bias, tip force, scanning speed and air humidity of the patterning environment. With multi-pixel scanning of SPL, we can control the pattern width and pattern height of local oxidation and then transfer these patterns onto the silicon substrate with wet etching. We have successfully demonstrated accurate linearity control of nanostructures fabrication for different linewidth from 25 to 77 nm by SPL technique. The resistivity of silicon substrate is around 1~10 ohm-cm. The diameter of silicon SPM tip is around 10 nm. Samples were hydrogen-passivated by dipping in 10% aqueous HF solution for 15 sec to remove surface native oxide before performing SPM local oxidation process. Then, anisotropic wet etching process was followed with a 34 wt.% aqueous KOH solution at 40°C for 45 sec. Utilizing the Orientation-Dependent Etching (ODE) of crystallographic planes and additional acoustic agitation, surface roughness can be reduced down to 3.28 nm, which is very close to that of RIE dry etching. Based on SPL and KOH wet etching techniques, EUV gratings nanostructures were demonstrated.

In this research, we investigate wet-etching properties of GaAs in NH₄OH-H₂O₂-H₂O and develop a novel bulk micromachining process for fabricating released micro-structures using (001) GaAs substrate. For obtaining wet-etching properties with respect to crystallographic orientation, the etch rates and undercut rates of (001) GaAs are measured using various compositions of NH₄OH-H₂O₂-H₂O mixed solutions. From these experimental data, a new GaAs micromachining method in bulk (001) GaAs is developed, and used to fabricate a released microbridges with a rectangular cross section. The developed GaAs micromachining method can be very useful for low-loss, highly-tunable capacitors for RF components and for integration with GaAs optical components.

X-ray lithography technology, suggested by Henry Smith in 1972, has been successfully under development for nearly 30 years, but it has not been applied in commercial IC production despite having a demonstrated resolution of 30 nm. This is connected with an unpredicted breakthrough in technology of photolithography to a fantastic resolution of 0.1 gm. Nevertheless, x-ray lithography could be the best choice for some new applications such as an extremely high resolution deep lithography for MEMS. In comparison with conventional photolithography, this new technique has no problems connected with the radiation scattering in a resist or reflection from a substrate and a mask, as well as standing waves and related swing curve effects, because of the x-rays nature. However x-ray lithography has some specific technological problems related with the exposure of the top and bottom resist layers with photoelectrons produced in a mask and a substrate during x-rays exposure.

A relatively little known form of photoresist coating or polymer application for special applications of 3-D structured wafer patterning and interconnection by spray technology has been studied. Specifically, the study was on the OmniSpray coating technology developed by Electronics Vision Group Austria [1,2]. Results of the present investigation confirm the superiority of the technique in comparison with the more conventional spin coating method in term of its ability to cover extreme 3-D structure conformally to enable 3-D patterning, and its significant reduction of expensive high-viscosity photoresist/polymer consumption for 3-D interconnect purposes. Special attention is paid to the improvement of photoresist coverage on the convex corners of the 3-D structure by rounding them off first in a TMAH solution, as well as the uniformity improvements in addition to the lower materials consumption for the application of intermediate layers for wafer interconnect purposes. The integrated method offers an enabling technology for patterning of extensive topography and wafer-level intermediate layer application typically required for a multitude of MEMS structures and designs, novel interconnect structures as well as advanced packaging applications. The method is simple, fast and low-cost in comparison with other photoresist coating techniques available and capable of 3-D structure patterning and interconnect.

A monolithic dielectric bolometer type uncooled infrared image sensor fabrication technology has been developed by integrating both Si bulk micromachining and ferroelectric thin film preparation technique. The operating principle of these dielectric bolometers has been explained and the fabrication process of the Si membrane structure and ferroelectric thin film have been elaborated. Metal Organic Decomposition (MOD) has been applied to prepare Barium Strontium Titanate (Ba_1−xSr_xTiO₃) ferroelectric thin film on micromachined Si wafer to fabricate the sensor. The detector pixel circuit is a capacitor-capacitor serially connected circuit, with one capacitor of BST film on Si membrane structure and the other on Si bulk structure. When irradiated by IR light, the capacitance of the IR detecting capacitor on membrane structure changed as a result of the change in dielectric constant against temperature of BST ferroelectric film. A stress-balanced structure of multi-layered membrane has been developed in order to avoid crack and deformation in the sensor fabrication process. Temperature Coefficient of Dielectric constant (TCD) of the MOD made BST (Ba:St 75:25) thin film is about 1%/K. Uniform and reproducible capacitance behaviours in the BST ferroelectric thin film capacitor on micromachined Si substrate have been confirmed. Chopperless operation has been attained and IR response evaluation of the fabricated sensor also has been carried out with R_v of 0.4 kV/W and D* of 9.8×10⁷ cmHz^l/2/W respectively.

A single-crystalline, single-wafer micro-gyroscope is fabricated using the Sur- face/Bulk Micromachining (SBM) process. The structural thickness of fabricated micro-gyroscope is 40 µm, and the sacrificial gap is 50 µm. For electrostatic actuation and capacitive sensing a new electrical isolation method, which uses a triple film composed of oxide, polysilicon and metal films, is developed. Two versions of gyroscopes are developed. In one version, the measured noise-equivalent angular rate resolution is 0.01°/sec, the input range is ±20°/sec, and the measured bandwidth is 16 Hz. In the second version, the measured values are 0.024^o/sec, ±50°/sec, and 33 Hz, respectively. The angle random walk for versions one and two are 0.0025°/ sec/√Hz and 0.0042°/sec/√Hz, respectively. These performance specifications put the SBM fabricated MEMS gyroscopes in the “tactical grade”.

This chapter describes an in-situ trench etching and release technique to fabricate high aspect-ratio beams for high performance MEMS accelerometers using the Sio₂ etching mask from Magnetically Enhanced Reactive Ion Etcher (MERLE). Work has started from comparison of the profiles of trenches masked by Sio₂ to those masked by Si₃N₄ in forming MEMS structures. In our experimental conditions using HBr/SiF₄/O₂ in MERLE, the etching process with the Sio₂ mask was proven to be able to form deeper anisotropic trenches than that with the the Si₃N₄ mask. Amount of oxygen available from the etching gas and/or the mask appeared to be a major factor controlling the floor etching of trenches as well as the sidewall passivation of beams. Excessive oxygen generated from the Sio₂ mask led to sidewall encroachment of the beams. On the other hand, lack of oxygen in the Si₃N₄ mask resulted in etch-stopping and micro-grassing, before forming the high-aspect-ratio MEMS structures. In the conventional process, lateral encroachment due to the release etching was severe underneath the Sio₂ mask. In the in-situ process developed in this research, the sidewall of the beams was passivated by inhibiting layers formed during the HBr/SiF₄/O₂ trench etching, and the beams were not attacked by the subsequent SF₆ release etching. Major constituents of the passivating layers that were produced by the in-situ process were Si and O. The in-situ process dispensed with both sidewall deposition and floor etching steps of the conventional process. Dependency of etching rates on open-ratio and pattern-size was studied in MERLE for high aspect-ratio MEMS structures. The etching rates of Si substrate in MERLE remained unchanged despite a change in the overall open-ratio on the wafer in the range of 10% to 50%, and this was different from the results of an ICE etcher.