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Journal of Electronic Testing

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29.05.2019

Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks

verfasst von: Ali Hajian, Saeed Safari

Erschienen in: Journal of Electronic Testing | Ausgabe 3/2019

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Abstract

With CMOS technology down-scaling, an assuring approach to reduce the power consumption of VLSI designs is Near-Threshold Computing (NTC). However, lowering the supply voltage continuously, exacerbates reliability challenges in modern CMOS logics due to creation of soft errors introduced by single event transients (SETs). In this work, we presented a fast-yet-accurate neural network based model to calculate soft error rate (SER) in circuits in the near-threshold voltage domain. Multi-Layer perceptron (MLP) and recurrent neural network (RNN) used for modeling each gate of a given library. The training data set includes injected SET samples, expected outputs and parameters of each gate. Finally, the propagation of faults in the investigated circuits is calculated using our proposed method. On average, experimental results show that we can estimate soft error rate 10-20 times faster in comparison to HSPICE simulation, with less than 0.1% accuracy loss.

Vorheriger Artikel Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique

Nächster Artikel Low Delay 3-Bit Burst Error Correction Codes

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Titel: Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks
verfasst von: Ali Hajian
Saeed Safari
Publikationsdatum: 29.05.2019
Verlag: Springer US
Erschienen in: Journal of Electronic Testing / Ausgabe 3/2019
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-019-05796-x

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