Skip to main content
Erschienen in: Journal of Computational Electronics 2/2019

12.01.2019

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

verfasst von: Pooja Bohara, Santosh Kumar Vishvakarma

Erschienen in: Journal of Computational Electronics | Ausgabe 2/2019

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

In this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 103 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Takeuchi, K.: Scaling challenges of NAND flash memory and hybrid memory system with storage class memory and NAND flash memory. In: IEEE Custom Integrated Circuits Conference, pp. 1–6 (2013) Takeuchi, K.: Scaling challenges of NAND flash memory and hybrid memory system with storage class memory and NAND flash memory. In: IEEE Custom Integrated Circuits Conference, pp. 1–6 (2013)
2.
Zurück zum Zitat Georgiev, V.P., Markov, S., Vilà-Nadal, L., Busche, C., Cronin, L., Asenov, A.: Optimization and evaluation of variability in the programming window of a flash cell with molecular metal–oxide storage. IEEE Trans. Electron Devices 61(6), 2019–2026 (2014)CrossRef Georgiev, V.P., Markov, S., Vilà-Nadal, L., Busche, C., Cronin, L., Asenov, A.: Optimization and evaluation of variability in the programming window of a flash cell with molecular metal–oxide storage. IEEE Trans. Electron Devices 61(6), 2019–2026 (2014)CrossRef
3.
Zurück zum Zitat Poliakov, P., Blomme, P., Pret, A.V., Corbalan, M.M., Gronheid, R., Verkest, D., Houdt, J.V., Dehaene, W.: Induced variability of cell-to-cell interference by line edge roughness in NAND flash arrays. IEEE Electron Device Lett. 33(2), 164–166 (2012)CrossRef Poliakov, P., Blomme, P., Pret, A.V., Corbalan, M.M., Gronheid, R., Verkest, D., Houdt, J.V., Dehaene, W.: Induced variability of cell-to-cell interference by line edge roughness in NAND flash arrays. IEEE Electron Device Lett. 33(2), 164–166 (2012)CrossRef
4.
Zurück zum Zitat Saha, S.K.: Scaling considerations for sub-90 nm split-gate flash. IET Circuits Devices Syst. 2(1), 144–150 (2008)CrossRef Saha, S.K.: Scaling considerations for sub-90 nm split-gate flash. IET Circuits Devices Syst. 2(1), 144–150 (2008)CrossRef
5.
Zurück zum Zitat Gelpey, J., McCoys, S., Kontos, A., Godet, L., Hatem, C., Camms, D., Chan, J., Papasouliotis, G., Scheuer, J.: Ultra-shallow junction formation using flash annealing and advanced doping techniques. In: International Workshop on Junction Technology, pp. 82–86 (2008) Gelpey, J., McCoys, S., Kontos, A., Godet, L., Hatem, C., Camms, D., Chan, J., Papasouliotis, G., Scheuer, J.: Ultra-shallow junction formation using flash annealing and advanced doping techniques. In: International Workshop on Junction Technology, pp. 82–86 (2008)
6.
Zurück zum Zitat Shima, A., Ashihara, H., Mine, T., Goto, Y., Horiuchi, M., Wang, Y., Talwar, S., Hiraiwa, A.: Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS. In: IEEE International Electron Devices Meeting, pp. 20.4.1–20.4.4 (2003) Shima, A., Ashihara, H., Mine, T., Goto, Y., Horiuchi, M., Wang, Y., Talwar, S., Hiraiwa, A.: Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS. In: IEEE International Electron Devices Meeting, pp. 20.4.1–20.4.4 (2003)
7.
Zurück zum Zitat Bang, T., Lee, B.H., Kim, C.K., Ahn, D.C., Jeon, S.B., Kang, M.H., Oh, J.S., Choi, Y.K.: Low-frequency noise characteristics in SONOS flash memory with vertically stacked nanowire FETs. IEEE Electron Device Lett. 38(1), 40–43 (2017)CrossRef Bang, T., Lee, B.H., Kim, C.K., Ahn, D.C., Jeon, S.B., Kang, M.H., Oh, J.S., Choi, Y.K.: Low-frequency noise characteristics in SONOS flash memory with vertically stacked nanowire FETs. IEEE Electron Device Lett. 38(1), 40–43 (2017)CrossRef
8.
Zurück zum Zitat Choi, S.J., Moon, D.-I.I., Kim, S., Ahn, J.H., Lee, J.S., Kim, J.Y., Choi, Y.K.: Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett. 32(5), 602–604 (2011)CrossRef Choi, S.J., Moon, D.-I.I., Kim, S., Ahn, J.H., Lee, J.S., Kim, J.Y., Choi, Y.K.: Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett. 32(5), 602–604 (2011)CrossRef
9.
Zurück zum Zitat Aldegunde, M., Martinez, A., Barker, J.R.: Study of discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulation. IEEE Trans. Electron Devices 33(2), 194–196 (2012)CrossRef Aldegunde, M., Martinez, A., Barker, J.R.: Study of discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulation. IEEE Trans. Electron Devices 33(2), 194–196 (2012)CrossRef
10.
Zurück zum Zitat Choi, S.J., Moon, D.-I.I., Kim, S., Duarte, J.P., Choi, Y.K.: Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32(2), 125–127 (2011)CrossRef Choi, S.J., Moon, D.-I.I., Kim, S., Duarte, J.P., Choi, Y.K.: Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Device Lett. 32(2), 125–127 (2011)CrossRef
11.
Zurück zum Zitat Chang, S.J., Bawedin, M., Xiong, W., Lee, J.H., Cristoloveanu, S.: FinFlash with buried storage ONO layer for flash memory application. Solid State Electron. 98, 59–66 (2012)CrossRef Chang, S.J., Bawedin, M., Xiong, W., Lee, J.H., Cristoloveanu, S.: FinFlash with buried storage ONO layer for flash memory application. Solid State Electron. 98, 59–66 (2012)CrossRef
12.
Zurück zum Zitat Jang, K.H., Jang, H.J., Park, J.K., Cho, W.J.: Self-amplified dual gate charge trap flash memory for low-voltage operation. IEEE Electron Device Lett. 34(6), 756–758 (2013)CrossRef Jang, K.H., Jang, H.J., Park, J.K., Cho, W.J.: Self-amplified dual gate charge trap flash memory for low-voltage operation. IEEE Electron Device Lett. 34(6), 756–758 (2013)CrossRef
13.
Zurück zum Zitat Choi, J.H., Yu, C.G., Park, J.T.: Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory. Microelectron. Reliab. 64, 215–219 (2016)CrossRef Choi, J.H., Yu, C.G., Park, J.T.: Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory. Microelectron. Reliab. 64, 215–219 (2016)CrossRef
14.
Zurück zum Zitat Micheloni, R. (ed.): 3D Flash Memories. Springer, Heidelberg (2016) Micheloni, R. (ed.): 3D Flash Memories. Springer, Heidelberg (2016)
15.
Zurück zum Zitat Micheloni, R., Crippa, L., Zambelli, C., Olivo, P.: Architectural and integration options for 3D NAND flash memories. Computers 6(3), 27 (2017)CrossRef Micheloni, R., Crippa, L., Zambelli, C., Olivo, P.: Architectural and integration options for 3D NAND flash memories. Computers 6(3), 27 (2017)CrossRef
16.
Zurück zum Zitat Jeong, M.K., Joe, S.M., Seo, C.S., Han, K.R., Choi, E., Park, S.K., Lee, J.H.: Analysis of random telegraph noise and low frequency noise properties in 3-D stacked NAND flash memory with tube-type poly-Si channel structure. In: Symposium on VLSI Technology (VLSI-Technology), Honolulu, HI, pp. 55–56 (2012) Jeong, M.K., Joe, S.M., Seo, C.S., Han, K.R., Choi, E., Park, S.K., Lee, J.H.: Analysis of random telegraph noise and low frequency noise properties in 3-D stacked NAND flash memory with tube-type poly-Si channel structure. In: Symposium on VLSI Technology (VLSI-Technology), Honolulu, HI, pp. 55–56 (2012)
17.
Zurück zum Zitat Kim, S.Y., Park, J.K., Hwang, W.S., Lee, S.J., Lee, K.H., Pyi, S.H., Cho, B.J.: Dependence of grain size on the performance of a polysilicon channel TFT for 3D NAND Flash memory. J. Nanosci. Nanotechnol. 16, 5044–5048 (2016)CrossRef Kim, S.Y., Park, J.K., Hwang, W.S., Lee, S.J., Lee, K.H., Pyi, S.H., Cho, B.J.: Dependence of grain size on the performance of a polysilicon channel TFT for 3D NAND Flash memory. J. Nanosci. Nanotechnol. 16, 5044–5048 (2016)CrossRef
18.
Zurück zum Zitat Li, X., Huo, Z., Jin, L., Wang, Y., Liu, J., Jiang, D., Yang, X., Liu, M.: Investigation of charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory. In: IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3 (2014) Li, X., Huo, Z., Jin, L., Wang, Y., Liu, J., Jiang, D., Yang, X., Liu, M.: Investigation of charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory. In: IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3 (2014)
19.
Zurück zum Zitat Yanagihara, Y., Miyaji, K., Takeuchi, K.: Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory, pp. 1–4. IEEE International Memory Workshop, Milan (2012) Yanagihara, Y., Miyaji, K., Takeuchi, K.: Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory, pp. 1–4. IEEE International Memory Workshop, Milan (2012)
20.
Zurück zum Zitat Jang, J., Kim, H.S., Cho, W., Cho, H., Kim, J., Shim, S.I., Younggoan Jeong, J.H., Son, B.K., Kim, D.W., Kihyun Shim, J.J., Lim, J.S., Kim, K.H., Yi, S.Y., Lim, J.Y., Chung, D., Moon, H.C., Hwang, S., Lee, J.W., Son, Y.H., Chung, U.I, Lee, W.S.: Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. In: Symposium on VLSI Technology, Honolulu, pp. 192–193 (2009) Jang, J., Kim, H.S., Cho, W., Cho, H., Kim, J., Shim, S.I., Younggoan Jeong, J.H., Son, B.K., Kim, D.W., Kihyun Shim, J.J., Lim, J.S., Kim, K.H., Yi, S.Y., Lim, J.Y., Chung, D., Moon, H.C., Hwang, S., Lee, J.W., Son, Y.H., Chung, U.I, Lee, W.S.: Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. In: Symposium on VLSI Technology, Honolulu, pp. 192–193 (2009)
21.
Zurück zum Zitat Hsiao, Y.H., Lue, H.T., Hsu, T.H., Hsieh, K.Y., Lu, C.Y.: A Critical Examination of 3D Stackable NAND Flash Memory Architectures by Simulation Study of the Scaling Capability, pp. 1–4. IEEE International Memory Workshop, Seoul (2010) Hsiao, Y.H., Lue, H.T., Hsu, T.H., Hsieh, K.Y., Lu, C.Y.: A Critical Examination of 3D Stackable NAND Flash Memory Architectures by Simulation Study of the Scaling Capability, pp. 1–4. IEEE International Memory Workshop, Seoul (2010)
22.
Zurück zum Zitat Yanagi, S., Nakakubo, A., Omura, Y.: Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime. IEEE Electron Device Lett. 22(6), 278–280 (2001)CrossRef Yanagi, S., Nakakubo, A., Omura, Y.: Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime. IEEE Electron Device Lett. 22(6), 278–280 (2001)CrossRef
23.
Zurück zum Zitat Beranger, C.F., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., Buttet, C.D., Gros, P., Nguyen, L.P., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.Y., Faynot, O., Skotnicki, T.: Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. In: Proceedings of ESSCIRC, pp. 88–91 (2009) Beranger, C.F., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., Buttet, C.D., Gros, P., Nguyen, L.P., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.Y., Faynot, O., Skotnicki, T.: Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. In: Proceedings of ESSCIRC, pp. 88–91 (2009)
24.
Zurück zum Zitat Kumar, M.J., Siva, M.: The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs. IEEE Trans. Electron Devices 55(6), 1554–1557 (2008)CrossRef Kumar, M.J., Siva, M.: The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs. IEEE Trans. Electron Devices 55(6), 1554–1557 (2008)CrossRef
25.
Zurück zum Zitat Yang, I.Y., Lochtefeld, A., Antoniadis, D.A.: Silicon-on-insulator-with-active-substrate (SOIAS) technology. In: IEEE International SOI Conference Proceedings, pp. 106–107 (1996) Yang, I.Y., Lochtefeld, A., Antoniadis, D.A.: Silicon-on-insulator-with-active-substrate (SOIAS) technology. In: IEEE International SOI Conference Proceedings, pp. 106–107 (1996)
26.
Zurück zum Zitat Yang, I.Y., Vieri, C., Chandrakasan, A., Antoniadis, D.A.: Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices 44(5), 822–831 (1997)CrossRef Yang, I.Y., Vieri, C., Chandrakasan, A., Antoniadis, D.A.: Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices 44(5), 822–831 (1997)CrossRef
27.
Zurück zum Zitat Ocker, J., Slesazeck, S., Mikolajick, T., Buschbeck, S., Günther, S., Yurchuk, E., Hoffmann, R., Beyer, V.: On the voltage scaling potential of SONOS non-volatile memory transistors. In: European Solid State Device Research Conference (ESSDERC), Graz, pp. 118–121 (2015) Ocker, J., Slesazeck, S., Mikolajick, T., Buschbeck, S., Günther, S., Yurchuk, E., Hoffmann, R., Beyer, V.: On the voltage scaling potential of SONOS non-volatile memory transistors. In: European Solid State Device Research Conference (ESSDERC), Graz, pp. 118–121 (2015)
28.
Zurück zum Zitat Wang, X., Kwong, D.L.: A novel high-κ SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation. IEEE Trans. Electron Devices 53(1), 78–82 (2006)CrossRef Wang, X., Kwong, D.L.: A novel high-κ SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation. IEEE Trans. Electron Devices 53(1), 78–82 (2006)CrossRef
29.
Zurück zum Zitat Wang, X., Liu, J., Bai, W., Kwong, D.L.: A novel MONOS-type nonvolatile memory using high-κ dielectrics for improved data retention and programming speed. IEEE Trans. Electron Devices 51(4), 597–602 (2004)CrossRef Wang, X., Liu, J., Bai, W., Kwong, D.L.: A novel MONOS-type nonvolatile memory using high-κ dielectrics for improved data retention and programming speed. IEEE Trans. Electron Devices 51(4), 597–602 (2004)CrossRef
30.
Zurück zum Zitat Lee, G.H., Yang, H.J., Jung, S.W., Choi, E.S., Park, S.K., Song, Y.H.: Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture. Jpn. J. Appl. Phys. 53, 014201 (2014)CrossRef Lee, G.H., Yang, H.J., Jung, S.W., Choi, E.S., Park, S.K., Song, Y.H.: Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture. Jpn. J. Appl. Phys. 53, 014201 (2014)CrossRef
31.
Zurück zum Zitat Hsu, T.H., Lue, H.T., Lai, S.C., King, Y.C., Hsieh, K,Y., Liu, R., Lu, C.Y.: Reliability of planar and FinFET SONOS devices for NAND flash applications—field enhancement versus barrier engineering. In: International Symposium on VLSI Technology, Systems, and Applications, pp. 154–155 (2009) Hsu, T.H., Lue, H.T., Lai, S.C., King, Y.C., Hsieh, K,Y., Liu, R., Lu, C.Y.: Reliability of planar and FinFET SONOS devices for NAND flash applications—field enhancement versus barrier engineering. In: International Symposium on VLSI Technology, Systems, and Applications, pp. 154–155 (2009)
32.
Zurück zum Zitat Sentaurus TCAD Manuals Synopsys. Inc. Mountain view, CA (2016) Sentaurus TCAD Manuals Synopsys. Inc. Mountain view, CA (2016)
33.
Zurück zum Zitat Lue, H.T., Wang, S.Y., Lai, E.K., Shih, Y.H., Lai, S.C., Yang, L.W., Chen, K.C., Joseph, K., Hsieh, K.Y., Rich, L., Lu, C.Y.: BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability. In: IEEE International Electron Devices Meeting, pp 547–550 (2005) Lue, H.T., Wang, S.Y., Lai, E.K., Shih, Y.H., Lai, S.C., Yang, L.W., Chen, K.C., Joseph, K., Hsieh, K.Y., Rich, L., Lu, C.Y.: BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability. In: IEEE International Electron Devices Meeting, pp 547–550 (2005)
34.
Zurück zum Zitat Gupta, D., Vishvakarma, S.K.: Improved short-channel characteristics with long data retention time in extreme short-channel flash memory devices. IEEE Trans. Electron Devices 63(2), 668–674 (2016)CrossRef Gupta, D., Vishvakarma, S.K.: Improved short-channel characteristics with long data retention time in extreme short-channel flash memory devices. IEEE Trans. Electron Devices 63(2), 668–674 (2016)CrossRef
35.
Zurück zum Zitat Gupta, D., Vishvakarma, S.K.: Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Trans. Device Mater. Reliab. 16(3), 298–303 (2016)CrossRef Gupta, D., Vishvakarma, S.K.: Impact of LDD depth variations on the performance characteristics of SONOS NAND flash device. IEEE Trans. Device Mater. Reliab. 16(3), 298–303 (2016)CrossRef
36.
Zurück zum Zitat Hsu, T.H., Lue, H.T., Hsieh, C.C., Lai, E.K., Lu, C.P., Hong, S.P., Wu. M.T., Hsu, F.H., Lien, N.Z., Hsieh, J.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Liu, R., Lu, C.Y.: Study of sub-30 nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application. In: IEEE International Electron Devices Meeting, pp. 1–4 (2009) Hsu, T.H., Lue, H.T., Hsieh, C.C., Lai, E.K., Lu, C.P., Hong, S.P., Wu. M.T., Hsu, F.H., Lien, N.Z., Hsieh, J.Y., Yang, L.W., Yang, T., Chen, K.C., Hsieh, K.Y., Liu, R., Lu, C.Y.: Study of sub-30 nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application. In: IEEE International Electron Devices Meeting, pp. 1–4 (2009)
37.
Zurück zum Zitat Conde, A.O., Sánchez, F.J.G., Liou, J.J., Cerdeira, A., Estrada, M., Yue, Y.: A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliab. 42(4–5), 583–596 (2002)CrossRef Conde, A.O., Sánchez, F.J.G., Liou, J.J., Cerdeira, A., Estrada, M., Yue, Y.: A review of recent MOSFET threshold voltage extraction methods. Microelectron. Reliab. 42(4–5), 583–596 (2002)CrossRef
38.
Zurück zum Zitat Colinge, J.-P.: Silicon-on-Insulator Technology: Materials to VLSI, 3rd edn. Springer, New York (2004)CrossRef Colinge, J.-P.: Silicon-on-Insulator Technology: Materials to VLSI, 3rd edn. Springer, New York (2004)CrossRef
Metadaten
Titel
NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention
verfasst von
Pooja Bohara
Santosh Kumar Vishvakarma
Publikationsdatum
12.01.2019
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 2/2019
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-018-01298-9

Weitere Artikel der Ausgabe 2/2019

Journal of Computational Electronics 2/2019 Zur Ausgabe

Neuer Inhalt