Neuro-inspired Computing Using Resistive Synaptic Devices

The biological brain has the capability of learning, pattern recognition, processing imprecisely defined data, and executing complex computational tasks. Consisting of 10¹¹ neurons and 10¹⁵ synapses as the major computational components, the biological brain is extremely power efficient, massively parallel, structurally plastic, and exceptionally robust against noise and variations (Kuzum et al. Nanotechnology 24:382001, 2013). The question of how to design and build a compact neuromorphic system is a grand challenge for academia and industry. An electronic synaptic device is an essential element in such neuromorphic systems. Among various electronic synapses candidates, nonvolatile memory-based synaptic devices have the highest potential to realize massive parallelism and 3D integration for achieving high function per unit volume. This chapter will focus on synaptic devices based on phase-change memory (PCM). We first review the basics of phase-change synaptic devices: device operation, phase-change materials, conduction mechanism, power consumption, and scaling. We then review the use of PCM synaptic device implementations spanning from single device operation to various array architecture designs in the following sections. The concept of spike-timing-dependent plasticity (STDP), various pulse scheme designs, and pulse programming techniques for plasticity will be explained and compared. Last, we will discuss recent advances in designing PCM synaptic device to achieve lower power consumption and more stable resistance states.

On the basis of its operation mechanism, the RRAM can be briefly classified as filamentary type and interfacial type. Comparing to the interfacial-type RRAM, faster switching speed and higher scalability of the filamentary-type RRAM have been demonstrated for NVM applications. However, considering previously discussed requirements of the synaptic device in Chap. 1, the interfacial-type RRAM is more proper than the filamentary-type RRAM exhibiting abrupt resistance changes. Thus, in this chapter, we focus on the interfacial-type RRAM for the synaptic device application. Among various interfacial-type RRAMs, especially Pr_0.7Ca_0.3MnO₃ (PCMO)-based RRAM which is demonstrated with wide on/off ratio, extremely stable and analog resistance change will be described. Firstly, feasibility of large-scale integration will be discussed for the synaptic device application. Then, we will move to synaptic characteristics of the PCMO-based RRAM. Lastly, various approaches that can improve synaptic characteristics will be introduced.

The development of a high-density, low-power, and reliable synaptic device is essential in the implementation of highly anticipated hardware neural networks. Hence, numerous studies have investigated suitable two-terminal synaptic devices that precisely mimic biological synaptic features. In this chapter, we reviewed the development of a Ta/TaO_x/TiO₂/Ti resistive switching memory (RRAM) as a promising synaptic device technology for future neuromorphic computing systems. First, we reviewed the basic memory characteristics of the device and introduced a switching mechanism through electrical measurements and physical simulations. Second, we found that the device was particularly suitable for analog synapses, where several synaptic characteristics were demonstrated; moreover, we built a compact model to simulate these characteristics. Finally, a three-dimensional (3D) synaptic network was realized. In this chapter, we discussed the nonlinear weight update of the device and proposed an identical pulse training scheme for its improvement.

Previous chapters have described the operation of nanoscale synaptic element at the single device level using experimental measurements. In this chapter, experimental demonstration of array-level associative learning using phase change synaptic devices is presented. The synaptic array is connected in a grid-like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. The system is robust to device variations, and large device-to-device variations in resistance states can be tolerated by increasing the number of training epochs. We illustrate the tradeoff between the ability of the network to tolerate variations and the overall energy consumption and found that energy consumption can be reduced if variation is lower.

Limitations of currently dominating von Neumann architectures have pushed the research toward brain-inspired solutions like neural networks to reach new levels of computing efficiency. While these highly parallelized architectures have achieved outstanding performances at software level, their hardware implementation is still a challenging problem due to the large amount of memory and arithmetic units required to store synaptic weights and implement synaptic transmission functions. One possible solution to tackle this challenging problem is to build neural networks with analog circuits and implement the functionality of synapses with the same nonvolatile memory unit that stores synaptic weights (a so-called in-memory computing). Scalability, analog behavior (multilevel programmability), speed, and power consumption are fundamental performance requirements for such memory arrays, given the huge number of synapses in state-of-the-art neural networks. Among different choices, Resistive Random Access Memories (RRAMs) are considered as one of the main candidates due to their excellent scalability and the possibility of their integration with fully mature CMOS technology. Here in this chapter, we will show the basic principles of such devices, alongside their performance as single devices and also when integrated in crossbars, all induced from experiments. We will also present the results of the first experimental realizations of single- and multi-layer neural networks with synapses implemented through crossbar arrays with detailed explanation on their in situ training. Finally, we conclude the chapter by presenting our recent progress on the 3D integration of resistive switching devices on top of CMOS-based circuitries and also by discussing the limitations of current implementations and future challenges.

Analog conductance of resistive random access memory (RRAM) is attractive for implementing the synaptic weights in neuro-inspired algorithms. One of the most popular deep learning algorithms is the convolutional neural network (CNN). The implementation of the convolution kernel on the resistive cross-point array is different than the implementation of the matrix-vector multiplication in prior works. In this chapter, we review our recent progress on offline weight tuning of the RRAM and its application for convolution kernel operation. First, we developed an optimized iterative programming protocol to tune the weights of HfO_x-based RRAM by adjusting the pulse amplitude incremental steps, the pulse width incremental steps, and the start voltages. Then, we demonstrated the key operation in the CNN—the convolution kernel on a 12 × 12 cross-point array. We proposed a dimensional reduction of 2D kernel matrix into 1D column vector, i.e., a column of the array, and enable the parallel readout of multiple 2D kernels simultaneously. As a proof-of-concept demonstration, we used the offline trained edge filters to detect both horizontal and vertical edges of the 20 × 20 pixels of black-and-white MNIST handwritten digits and the 50 × 50 pixels of a grayscale “dog” image on a 12 × 12 resistive cross-point array based on the HfO_x RRAM. The experimental results of the kernel operation perfectly match the simulation results, indicating the feasibility of the proposed implementation methodology of the convolution kernel on the resistive cross-point array for future large-scale integration.

Spiking neural network has potential to provide power efficiency and additional functionality compared to conventional artificial neural network (ANN) due to its distinctive features such as spike representation and computation capability using time. The incompatibility of spiking neural network (SNN) to conventional von Neumann computing architecture necessitates development of novel computing architecture for spiking neural network. Neuromorphic computing architecture with nonvolatile memory devices storing synaptic weights can lead to area- and power-efficient hardware implementation for spiking neural network. We will discuss one such neuromorphic chip implementation which has 256 on-chip neuron circuits and 64 k PCM synaptic cells with on-chip learning capability. The two-transistor one-resistor synaptic unit cell structure enables each synaptic cell in the array to operate in asynchronous and parallel fashion, which facilitates scaling up to a larger neural network.

Peripheral circuits in the resistive synaptic arrays perform the function of neurons in neuro-inspired computing applications and are responsible for the read and write operations of resistive device arrays. The read operation in resistive arrays essentially performs the weighted sum or inner-product computation, which is the most critical operation in neural networks. On the other hand, the write operation is accountable for updating resistive synapse weights, which is the key operation for learning in neural networks. To efficiently enable these read and write operations in resistive arrays, a number of different design techniques in literature will be presented in this chapter. First the CMOS circuit implementations for the read operation and the write operation will be examined, and then recent non-CMOS circuit implementations will also be described. Advantages, trade-offs, and future design prospects of different peripheral circuit designs will be discussed.

There has been a lot of work on accelerating neuro-inspired algorithms on the platforms of GPU, FPGA, and ASIC. Most prior work lies in the traditional processor-coprocessor architecture, in which data are accessed from main memory in a conventional way. This chapter introduces a novel processing-in-memory (PIM) architecture based on the resistive crossbar array structure for accelerating neuro-inspired algorithms, called PRIME. As the computing paradigm shifts from the computation-centric to the data-centric, PIM or near data computing (NDC) has become a promising solution to address the “memory wall” challenges by placing computation capabilities in or near memory. PRIME is a PIM architecture based on RRAM main memory design. It moves the computing resources to the memory side by adapting a portion of RRAM crossbar arrays in the main memory for efficient weighted sum and weight update operations in neuro-inspired algorithms. Moreover, it provides a set of circuit and microarchitecture design as well as system-level support to implement various deep neural networks (DNNs). Benefiting from both the PIM architecture and the efficiency of using RRAM crossbar arrays for neuro-inspired computing, PRIME can achieve significant performance improvement and energy saving compared with prior hardware acceleration work.

Large arrays of the same nonvolatile memories (NVMs) being developed for storage-class memory (SCM) – such as phase-change memory (PCM) and resistive RAM (RRAM) – can also be used in non-Von Neumann neuromorphic computational schemes, with device conductance serving as synaptic “weight.” This allows the all-important multiply-accumulate operation within these algorithms to be performed efficiently at the weight data.

In contrast to other groups working on spike-timing-dependent plasticity (STDP), we have been exploring the use of NVM and other inherently analog devices for artificial neural networks (ANN) trained with the backpropagation algorithm. We recently showed a large-scale (165,000 two-PCM synapses) hardware/software demo (IEDM 2014) and analyzed the potential speed and power advantages over GPU-based training (IEDM 2015).

In this chapter, we extend this work in several useful directions. In order to develop an intuitive understanding of the impact that various features of such jump tables have on the classification performance in the ANN application, we describe studies of various artificially constructed jump tables. We then assess the impact of undesired, time-varying conductance change, including drift in PCM and leakage of analog CMOS capacitors. We investigate the use of nonfilamentary, bidirectional RRAM devices based on PrCaMnO₃, with an eye to developing material variants that provide sufficiently linear conductance change. And finally, we explore trade-offs in designing peripheral circuitry, balancing simplicity and area efficiency against the impact on ANN performance.

The sparse coding is an unsupervised algorithm that can efficiently extract the features from the input dataset. However, the learning accuracy can be potentially hampered by several limiting factors of the resistive synaptic device behaviors, including the nonlinearity and device variations in weight update, and the read noise, limited ON/OFF weight ratio and array parasitics in weighted sum. This book chapter employs device-algorithm co-design methodologies to quantify and mitigate the impact of these nonideal properties on the learning accuracy at the system level. It is observed that the realistic device behaviors in the weight update are tolerable, while those in the weighted sum are detrimental to the accuracy. The strategies to mitigate this accuracy loss include (1) multiple cells as a synapse to alleviate the impact of device variations, (2) a dummy column at minimum conductance to eliminate the off-state current, and (3) selector and larger array wire width to reduce IR drop along interconnects.

This chapter describes an artificial synapse composed of multiple binary resistive RAM (RRAM) cells connected in parallel, thereby providing synaptic analog behavior. The vertical RRAM technology is presented as a possible solution to gain area by realizing one pillar per synapse. First, the proposed synapse has been used for the implementation of power efficient Convolutional Neural Networks for visual pattern recognition with supervised learning. This architecture is suitable for embedded hardware implementation in portable devices, thereby eliminating the latency to cloud access and avoiding the large energy cost per bit transmitted through the cloud. Second, the RRAM-based synapse coupled with unsupervised learning has been proposed to perform real-time decoding (spike sorting) of complex brain signals using a RRAM-based fully connected neural network. This approach coupled with brain-machine interfaces (BMIs) may enable the design of prosthetic devices that require to extract and decode in situ information from very large numbers of neurons without transmitting and processing this information offline.