An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data

The high speed wireline communication suffers from a lot of signal quality issues such as jitter and swing, which eventually leads to higher probability of data loss. As the current mode multiplexer, being the integral cell of any transceiver circuit guides to Serialize data in high rate, its arrangement is of utmost importance. This work explores a novel configuration of multiplexer embedded with cross-coupled NMOS latch after integrating the Transmission Gate (TG) principle with the MOS Current Mode Logic (MCML). The proposed configuration reads an average power, delay and power-delay product (PDP) of as tiny as 135.7 μW, 20.16 ps and 2.736 fJ, respectively when simulated for 90 nm CMOS using Cadence Virtuoso at 10 GHz switching frequency and 1 V power supply. The process variation is performed at different corners through Monte-Carlo runs with ‘no skew’ and ‘5% process skew’ variation at both pre-layout and post-layout to prove the robustness of the proposed Mux-Latch, which is employed to tender a new low gate count and energy efficient variation aware Serializer circuit capable of offering a data rate of as high as 50 Gbit/s. The entire circuit is also validated at lower technology nodes like 28 nm UMC.