An improved CMOS-based inductor simulator with simplified structure for low-frequency applications

Inductance is a vital component for many analog and mixed-signal circuits and systems. Large inductances are often needed if operational frequency of a circuit is not very high, but they are difficult to be integrated into an integrated circuit (IC) due to the large chip area required. There have been a number of attempts to develop inductor simulators, which can perform the analog function of inductance [1‐12]. The most commonly used structures of these inductor simulators are composed of multiple passive components and complicated operational modules such as current conveyor (CC) [2‐5], current feedback operational amplifier (CFOA) [6], operational trans-conductance amplifier (OTA) [7], current backward trans-conductance amplifier (CBTA) [8] and current differencing buffered amplifier (CDBA) [9]. This is because that they attempt to achieve functional flexibility, i.e., to be reconfigured to form other circuit functions such as frequency dependent negative resistor (FDNR), while aiming at low-frequency applications. Other structures [10‐12] use fewer and less complicated components to be structurally simple and to minimize the effect of parasitic parameters. However, these are primarily used for high-frequency or RF applications. In this paper, an improved structure for grounded inductor composed of only five active components and one capacitor for low-frequency applications is proposed. Compared to the structure in [1] which was proposed for the same purpose, this structure is further simplified and is able to simulate the same or comparable inductance value with smaller capacitor and wider operational frequency bandwidth. In addition, by adding only three more transistors to the structure, the grounded inductor simulator can be easily upgraded to floating inductor simulator.

The rest of this paper is organized as follows: Section 2 presents the process of designing inductor simulator. Section 3 shows simulation results and analysis of the proposed inductor simulators. Finally, conclusions are drawn in Sect. 4.

To achieve simplified structure and simulate a range of inductance values at low operational frequency, MOSFET is to be used as prime component rather than CC or OTA. The design method is based on the nullator–norator technique. A nullator represents a port that has no potential difference across its two terminals and has no current flowing into or out of it, as shown in Fig. 1a. A norator represents a port that has arbitrary current flowing through and has arbitrary potential difference across its two terminals, as shown in Fig. 1b. The nullator–norator models of second generation current conveyor (CCII) and MOSFET are shown in Fig. 1c, d [5]. Figure 1 illustrates clearly the structural similarity between CCII and MOSFET, which suggests that instead of CCII, MOSFET may be used to construct an inductor simulator.

There are two key components that are used to build the proposed inductor simulator, MOSFET and capacitor. MOSFET is used to convert voltage signal into current signal. The capacitor is used to emulate voltage–current characteristic of inductor, i.e., [13]where \(V_\mathrm{{C}}\) and \(I_\mathrm{{C}}\) are the voltage and the current applied to capacitor, \(V_\mathrm{{sim}}\) and \(I_\mathrm{{sim}}\) are the voltage and the current applied to inductor, \(X_\mathrm{{C}}\) is the value of the capacitor, \(X_\mathrm{{L}}\) is the value of the inductor, \(\omega \) is operational frequency, and j is the imaginary unit representing 90-degree phase shift. It is obvious from Eq. (1) that if \(X_\mathrm{{C}} =X_\mathrm{{L}}\), the impedance of the capacitor is reciprocal of the inductor’s impedance.

To realize simulation of inductor, an inductor simulator is constructed here using a two-port operational module, as shown in Fig. 2. One port (PORT 1) of the module connects to a capacitor C0. The other port (PORT 2) connects to an arbitrary external circuit. The function of this operational module is to make \(V_\mathrm{{sim}} /I_\mathrm{{sim}}\) equal to \(I_\mathrm{{C}} /V_\mathrm{{C}} \), so that the impedance of the simulated inductor \((V_\mathrm{{sim}} /I_\mathrm{{sim}} )\) is the same as the reciprocal of the impedance of the capacitor C0. It operates as follows: Once the voltage \(V_\mathrm{{sim}}\) is applied onto PORT 2, the current \(I_\mathrm{{C}}\) that is proportional to \(V_\mathrm{{sim}}\) is generated and fed into the capacitor C0 in PORT 1, therefore producing the voltage \(V_\mathrm{{C}}\) across the capacitor. Then from the \(V_\mathrm{{C}} \), the current \(I_\mathrm{{sim}}\) that is proportional to \(V_\mathrm{{C}}\) is generated and fed back into PORT 2.

Following the working explained above, the nullator–norator structure of the inductor simulator is acquired, as shown in Fig. 3.

The relationship between the port voltage \(V_\mathrm{{sim}}\) and the port current \(I_\mathrm{{sim}}\) can be deduced as [14]where \(L_\mathrm{{sim}} =\frac{g_{m2} }{g_{m1} g_{m3} g_{m4} }C0\) is the inductor to be simulated through the capacitor C0. By replacing the nullator–norator pairs in Fig. 3 with MOSFETs, we can obtain the grounded inductor simulator circuit, as shown in Fig. 4. The gm1, gm2, gm3,  and gm4 in Fig. 3 are trans-conductances of the MOSFETs M1, M2, M3, and M4 in Fig. 4, respectively. The MOSFET M5 is to provide a current bias for the circuit.

In order to consider the main parasitic parameters that will affect the frequency response of the circuit, Eq. (2) needs to be modified by taking parasitic capacitance and output resistance of MOSFETs into account [14], and then it becomeswhere \(G_m =\frac{g_{m1} g_{m3} g_{m4} }{g_{m2} }\) is the open loop trans-conductance, \(R_{\mathrm{{O}}35} =R_{\mathrm{{O}}3} |R_{\mathrm{{O}}5}\) is the resultant resistance of the output resistance of M3 \((R_{\mathrm{{O}}3} )\) and the output resistance of M5 \((R_{\mathrm{{O}}5} )\) in parallel connection, \(R_{\mathrm{{O}}4}\) is the output resistance of M4, \(C_{\mathrm{{gs}}}\) and \(C_{\mathrm{{ds}}}\) are the gate-source parasitic capacitance and the drain-source parasitic capacitance of MOSFET, respectively, and \(\omega _0 =g_{m2} /\left( {C_{\mathrm{{gs}}2} + C_{\mathrm{{gs}}3} + C_{\mathrm{{ds}}2} + C_{\mathrm{{ds}}1} } \right) \) and \(\omega _1 =1/R_{\mathrm{{O}}35} C0\) are the two poles of the open loop transfer function. The \(\omega _0\) is always a very high-frequency pole, which is normally negligible.

According to the conventional calculations [14], if the frequency \(\omega >10\omega _1\), Eq. (3) can be simplified aswhereIf the frequency \(\omega <10\omega _1 \), Eq. (3) can be simplified aswhereEquations (4) and (5) mean that the circuit in Fig. 4 can be simplified to one of the two equivalent circuits shown in Fig. 5. Figure 5a shows the equivalent inductor simulator circuit operating at high frequency, which is derived through Eq. (4). Figure 5b shows the equivalent inductor simulator circuit operating at low frequency, which is derived through Eq. (5).

From Eqs. (4) and (5) as well as Fig. 5, it is easy to understand that the frequency range of equivalent circuit is determined by \(C_\mathrm{{sim}}\) at high frequency and by \(R_\mathrm{{s}}\) at low frequency. This is because that the \(C_\mathrm{{sim}}\) together with \(L_{\mathrm{{sim}}}\) will form a double-pole point (or resonation point), which prevents magnitude response from keeping rising up, and that the \(R_\mathrm{{s}}\) together with \(L_\mathrm{{sim}}\) will form a zero point, which prevents magnitude response from keeping going down. Hence, the upper and lower limits of the operational frequency are decided by the following double-pole point \(\omega _\mathrm{{D-pole}}\) and zero point \(\omega _\mathrm{{Zero}}\), respectively:Furthermore, by replacing the V \(_\mathrm{{bias} }\) terminal in Fig. 4 with another grounded inductor simulator, a floating inductor simulator can be acquired, as shown in Fig. 6. This floating inductor simulator has the same function and electrical characteristics as the grounded inductor simulator in Fig. 4, but it is more flexible in terms of its applications since both of its terminals can be connected to other circuits.

The circuit of Fig. 4 is simulated using the configuration shown in Fig. 7. The terminal   \(V_{\mathrm{{bias}}}\) connects to a voltage source \(V_\mathrm{{S}}\) to provide DC voltage bias for the MOSFET M5. The terminal \(V_{\mathrm{{sim}}}\) connects to a current source \(I_\mathrm{{S}}\) to provide the DC current bias \(I_\mathrm{{bias}}\) for the MOSFET M4 and to provide the AC signal excitation \(I_\mathrm{{sim}}\) as well. The bulks of NMOS and PMOS transistors are connected to the ground GND and the power supply VCC, respectively. The simulations are performed using SPICE based on 0.5 \(\upmu \)m CMOS process BSIM3v3 model (the threshold voltages of NMOS and PMOS are \(V_{\mathrm{{TN0}}}= 0.7619\) V and \(V_{\mathrm{{TP0}}}= -0.9570\) V, respectively; the electron mobility and hole mobility are \(u_{0N}= 861.083\,\mathrm{{cm}}^{2}/\hbox {V\,s}\) and \(u_{0P}= 568.314\,\mathrm{{cm}}^{2}/\hbox {V\,s}\), respectively; the thickness of gate oxide is \(T_{\mathrm{{OX}}}= 25\) nm). The dimensions of the CMOS transistors \((\hbox {M1}{-}\hbox {M5})\) used in the implementation are given in Table 1. To test the functionality of the circuit in Fig. 4, three types of constructions of the circuit with different sizes of components (Type-1, Type-2, and Type-3) are simulated, as shown in the table, so that a variety of inductor values with their corresponding operational frequency ranges can be produced.

The floating inductor simulator in Fig. 6 has the same simulation results as the grounded inductor simulator in Fig. 4, with the transistors \(\hbox {M6}{-}\hbox {M8}\) having the same dimensions as the transistors \(\hbox {M3}{-}\hbox {M5}\).

From the simulation results, it is obvious that compared to an ideal inductor which has no frequency restriction, the simulated inductors work within certain limited frequency range. Taken the Type-2 (35 mH) of the circuit as an example, the magnitude responses of the frequency domain simulations in Fig. 8 show that the circuit has a zero point at 620 Hz and a double-pole point at 4.6 MHz, which are determined by \(R_\mathrm{{s}}\) and \(C_{\mathrm{{sim}}}\), respectively. This is in accordance with the theoretical analysis of the frequency limits described in Sect. 2. The phase responses of the frequency domain simulations are given in Fig. 9, which shows that the zero point of 620 Hz and the double-pole point of 4.6 MHz yield an actual working frequency range from 6.2 kHz \((10\omega _\mathrm{{Zero}})\) to 2.3 MHz (calculated through \(R_{\mathrm{{S}}}\) and \(\omega _\mathrm{{D-pole}}\)).

To compare with the similar structures proposed recently [1, 3, 7, 9], Table 2 is compiled, in which the area is calculated by only taking capacitor into account, as it consumes most of the chip area. It is assumed that 1 fF capacitance takes 1 \(\upmu \hbox {m}^{2}\) of chip area. The test conditions (bias) and the power consumptions under these conditions are also given.

Table 2 shows that among the similar structures compared, this structure uses the least number of MOSFETs (only 5 for grounded inductor), leading to the simplest circuit. It is capable of simulating a broad range of inductance values that are covered by all other structures. Meanwhile, for the same or comparable inductance value, its operational frequency bandwidth is much wider (e.g., for 1.0 H inductor, Type 1 of this work and Ref. [9] have a bandwidth of 868.2 Hz and 10 kHz, respectively). However, the proposed structure does not operate at as low frequency as others do (e.g., Type 3 of this work and Ref. [3] with the same inductance value of 1.5 mH have a minimum operational frequency of 79.5 Hz and 15 KHz, respectively), since it uses much smaller capacitors (no more than 10 pF) in order to significantly reduce chip area as shown in the table.

This paper describes an improved structure for inductor simulator to be used in CMOS integrated circuits for low-frequency applications. The structure features low component count and use of small capacitance, thus resulting in simplified circuit structure and much reduced chip area. The simulation results demonstrate that this structure not only can produce a broad range of inductance values but also compared to other similar structures, it provides wider operational frequency bandwidth for the same/comparable inductance value. Moreover, the structure is implemented with significantly reduced chip area using a small capacitor in the circuit, but this is at the cost of having a higher minimum operational frequency compared to other structures.