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Erschienen in: Theory of Computing Systems 2/2016

01.08.2016

Complexity of Fixed-Size Bit-Vector Logics

verfasst von: Gergely Kovásznai, Andreas Fröhlich, Armin Biere

Erschienen in: Theory of Computing Systems | Ausgabe 2/2016

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Abstract

Bit-precise reasoning is important for many practical applications of Satisfiability Modulo Theories (SMT). In recent years, efficient approaches for solving fixed-size bit-vector formulas have been developed. From the theoretical point of view, only few results on the complexity of fixed-size bit-vector logics have been published. Some of these results only hold if unary encoding on the bit-width of bit-vectors is used. In our previous work (Kovásznai et al. 2012), we have already shown that binary encoding adds more expressiveness to various fixed-size bit-vector logics with and without quantification. In a follow-up work (Fröhlich et al. 2013), we then gave additional complexity results for several fragments of the quantifier-free case. In this paper, we revisit our complexity results from (Fröhlich et al. 2013; Kovásznai et al. 2012) and go into more detail when specifying the underlying logics and presenting the proofs. We give a better insight in where the additional expressiveness of binary encoding comes from. In order to do this, we bring together our previous work and propose several new complexity results for new fragments and extensions of earlier bit-vector logics. We also discuss the expressiveness of various bit-vector operations in more detail. Altogether, we provide the currently most complete overview on the complexity of common bit-vector logics.

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Fußnoten
2
This kind of result is often called unary NP-completeness [32].
 
3
Recall that only a variable, a constant, or an uninterpreted function can have explicit bit-width.
 
4
Although we do not intend the present a reduction of a general shift to the respective shift by constant, it is worth to mention that a common approach for such a reduction is the barrel shifter.
 
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Metadaten
Titel
Complexity of Fixed-Size Bit-Vector Logics
verfasst von
Gergely Kovásznai
Andreas Fröhlich
Armin Biere
Publikationsdatum
01.08.2016
Verlag
Springer US
Erschienen in
Theory of Computing Systems / Ausgabe 2/2016
Print ISSN: 1432-4350
Elektronische ISSN: 1433-0490
DOI
https://doi.org/10.1007/s00224-015-9653-1

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