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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 4/2017

31.08.2017 | S.I.: Computational Electronics of Emerging Memory Elements

Cross-point memory design challenges and survey of selector device characteristics

verfasst von: Xiaochen Peng, Ryan Madler, Pai-Yu Chen, Shimeng Yu

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2017

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Abstract

In this survey, the design challenges of cross-point memory arrays with emerging nonvolatile memory technologies are discussed. In particular, the write/read scheme for cross-point memory and the associated problems such as voltage drop along interconnect and sneak path current via unselected cells are analyzed. The write voltage margin and power consumption, as well as the read-current sensing margin and latency, are simulated with a voltage-mode sense amplifier for different array sizes and nonlinearity of the selector devices. Finally, state-of-the-art performance and mechanism of selector devices are summarized and they are classified as Type I selector with exponential current–voltage (I–V) characteristics and Type II selector with threshold I–V characteristics. Design challenges and device engineering guidelines are discussed for both types of selector in the summary.
Vorheriger Artikel Stochastic circuit breaker network model for bipolar resistance switching memories
Nächster Artikel Design rules for threshold switches based on a field triggered thermal runaway mechanism

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Metadaten
Titel
Cross-point memory design challenges and survey of selector device characteristics
verfasst von
Xiaochen Peng
Ryan Madler
Pai-Yu Chen
Shimeng Yu
Publikationsdatum
31.08.2017
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 4/2017
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-017-1062-z

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