Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata

A quantum-dot cellular automaton is a new technology that solves all the disputes CMOS technology faces. Quantum-dot cellular automata-based computations run at ultra-high speeds with very high device density and low power consumption. Reversible logic design, featured in quantum-dot cellular automata, permits fully invertible computation. The arithmetic and logic units are the major components in all microprocessor-based systems that probably serve as the processing device's heart. This paper discusses an area-efficient quantum-dot cellular automata technology-based coplanar, reversible arithmetic and logic unit using the double Peres and Feynman gates. With a latency of \(2.5\) clocks and a total area of 0.1 μm², the proposed arithmetic and logic unit performs 19 logic and arithmetic operations. QCA Designer and QD-E are used to simulate the proposed design and energy consumption, respectively. The proposed design's total energy dissipation, as measured by QCA Designer-E, is 5.45e−002 eV, and the average energy dissipation is 4.95e−003 eV. The proposed method has a considerable number of improvements in terms of latency, the number of operations, and area compared to earlier work.