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Journal of Electronic Testing

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04.02.2019

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

verfasst von: Paulo R. C. Villa, Rodrigo Travessini, Roger C. Goerl, Fabian L. Vargas, Eduardo A. Bezerra

Erschienen in: Journal of Electronic Testing | Ausgabe 1/2019

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Abstract

Embedded soft-core processors are becoming the usual solution to deal with network and data communications inside FPGAs. However, when developing space-based applications, the designer must consider the effects of ionizing radiation such as Total Ionizing Dose (TID) and Single-Event Effect (SEE). The majority of techniques for mitigation of Single-Event Upsets (SEUs) on FPGAs are based on hardware spatial-redundancy. This work presents a fault-tolerance technique, based on the concept of temporal redundancy, with checkpoints and recovery for soft-core processors. The proposed modified architecture is aimed at embedded systems for space applications based on FPGAs. Our experimental results show that the Checkpoint Recovery technique is a valid alternative to traditional spatial-redundancy, especially when considering limited logic area and power budget present on a satellite. The results present levels of reliability comparable to those of the more conventional fault-tolerance techniques. Additionally, the proposed approach does not require modifications of the software source code or compiler.

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Titel: Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy
verfasst von: Paulo R. C. Villa
Rodrigo Travessini
Roger C. Goerl
Fabian L. Vargas
Eduardo A. Bezerra
Publikationsdatum: 04.02.2019
Verlag: Springer US
Erschienen in: Journal of Electronic Testing / Ausgabe 1/2019
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-019-05778-z

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