Scientific complications and controversies noted in the field of CdS/CdTe thin film solar cells and the way forward for further development

The literature shows that there are several different growth techniques used for the growth of CdS layers. Most popular techniques are the chemical bath deposition (CBD), close-space sublimation (CSS), sputtering and electrodeposition (ED). For the growth of CdTe layers, there are about 14 different growth techniques [24], but the commercially successful methods have been CSS and electrodeposition (ED). First Solar Company is successfully using modified CSS to produce high-efficiency devices, and the manufacturability of ED-CdTe has also been successfully proven by BP Solar [15]. Because of the comprehensive research carried out by the authors of this article on electrodeposition of semiconductors, most of the examples given in this paper will be based on ED-CdTe thin films [25, 26], but the principles can also be applied to CdTe layers grown by other techniques.

The main results explored to date for electroplated CdTe are summarised in Fig. 1 [27]. An electrolyte containing Cd-ions and Te-ions can be used for electroplating CdTe thin films using either 2-electrode or 3-electrode systems and both methods produce key features shown in Fig. 1 [28]. Figure 1 summarises the variation in crystallinity (XRD), electrical conduction type (photoelectrochemical (PEC) signal), doping concentrations and possible defects as a function of the growth voltage (V_g). Since the redox potential (E°) with respect to hydrogen electrode, E° values for Te is + 0.59 V and Cd is − 0.40 V; the easiest element to electrodeposit is Te. At a certain voltage (V_i) for a given electrolyte, stoichiometric CdTe (Cd:Te = 1:1) is produced showing the highest crystallinity as shown by curve A. The curve A shows the variation in the intensity of the strongest XRD peak (111) of CdTe layers as a function of growth voltage, V_g. The V_i for this particular electrolyte is 1.576 V (for a 2-electrode deposition set-up), and this value changes according to the composition of the electrolyte and the number and nature of electrodes used. As shown by the curve BiB’, produced using the photo-electro-chemical (PEC) cell results, the materials grown at V_g less than V_i are rich in Te and produce p-type CdTe. The layers grown at V_g greater than V_i are rich in Cd and produce n-type CdTe. Therefore, CdTe is a material that can be intrinsically doped during growth by changing the stoichiometry of the material. This intrinsic property is not only limited to electroplating but also should be valid for any CdTe growth technique. Curve CiC’ indicates some possible doping concentrations as a function of growth voltage, V_g, and possible native defects are also indicated in Fig. 1, for two types of different CdTe layers. These trends have been observed and repeated numerous times by authors’ group using different precursors in the ED bath. This phenomenon of variable conduction properties based on compositional ratio is eminent in CSS-grown CdTe too, as discussed in the later sections.

Since Te is the easier element to electrodeposit, it has been identified that Te-precipitation takes place at nanoscale, and this has been reported before for electroplated CdTe thin films [29]. Not only in ED-CdTe thin films, but also in CSS-CdTe thin films and melt-grown bulk CdTe, Te-precipitation has been observed [30‐32]. This indicates that the Te-precipitation in CdTe is a natural feature and tends to produce p-type CdTe layers. As presented in later sections of this paper, n-type CdTe is more suitable for fabricating high-efficiency devices, and therefore, methods to prevent the formation of Te-precipitation should be established. Fernandez et al. [32] have shown that the incorporation of Ga removes Te-precipitates from CdTe. The positive effects of Ga incorporation on thin film CdTe solar cell efficiencies have been reported by Ojo et al. [33]. Though this is not particularly a controversy, yet related research on preventing Te-precipitation in CdTe layers should be encouraged to develop CdS/CdTe solar cells further.

Intrinsic doping of CdTe is described using Fig. 1, in the above section by changing the Cd and Te compositions in ppm level. Another method to improve the electrical conduction in CdTe is extrinsic doping by adding selected external dopants into the material. For example, group-III (B, Al, Ga, In, …) and group-VII (halogens—F, Cl, Br, I) elements are suitable n-type dopants for CdTe [34]. The positive results have been certainly observed with Ga and halogens (Cl, F and I). Similarly, group-I (Li, Na, K, Ag, Cu,…) and group-V (P, As, Sb, Bi,…) elements are suitable p-type dopants for CdTe [22]. The literature reports ~ 10¹³–10¹⁵ cm⁻³ doping concentration for high-efficiency CdS/CdTe solar cells [13, 35‐37]. Future research should be directed to increase these doping concentrations to ~ 10¹⁵–10¹⁶ cm⁻³ to improve CdS/CdTe solar cell performance, and extrinsic doping can play a vital role here. But unfortunately, the self-compensation mechanism due to native defects is high in CdTe, and therefore, the addition of these dopants does not always behave according to solid-state physics principles. Therefore, extrinsic doping of CdTe, if necessary, should be carried out with thorough understanding.

Cadmium chloride treatment or the activation step is a well-known processing step to increase the efficiency of CdS/CdTe thin film solar cells [38‐41]. Numerous publications are available on this treatment that includes the introduction of CdCl₂ on to the CdTe surface and heat treatment in air at an optimised temperature for optimised time period. After a suitable chemical etching, an electrical contact is deposited to complete the glass/TCO/CdS/CdTe/electrical contact, solar cell. The research community agrees on changes such as grain growth, defects removal, grain boundary passivation and interactions at the CdS/CdTe interface during this CdCl₂ heat treatment. As a result of this processing step, a drastic improvement in the device efficiency has been observed. However, the fine details of this processing step are not yet fully understood. More focussed research should be carried out in order to understand the fine details of these named areas.

The following section summarises the authors’ work on “defects removal” in ED-CdTe thin films. Photoluminescence (PL) has been used in the past to identify defects in the material. However, due to instrumental limitations, most of the PL systems detect defect levels close to the band-to-band transitions. In our previous work [42], a wider energy range from (E_c–0.50) to E_v was explored for defects structure using PL. Figure 2 shows the PL spectra and the defect structure for as-deposited (AD) and CdCl₂ treated CdTe layers in this wide energy range. It is clear that the bandgap of AD-CdTe is full of defects and most of these reduce during CdCl₂ treatment. More importantly, the mid-gap defect level at ~ 0.74 eV is the most responsible one for recombination and generation (R&G) process within the devices and should be minimised or completely removed to increase the device performance. Future research should be focussed, on reduction or if possible removal of these defects completely. This is a major step to improve the device performance further.

This work shows that the CdCl₂ treatment reduces a very broad mid-gap defects distribution to a comparatively narrow mid-gap defect level ~ 0.74 eV. The origin of these defects is not very clear, and these could be due to intrinsic defects or extrinsic defects due to inclusion of an unknown impurity into the crystal lattice. However, the PL work reported in ref. [17] for chemically etched CdTe surfaces indicates that these mid-gap defects level appears for Te-rich CdTe surfaces. This is helpful in drawing conclusions on mid-gap defects at ~ 0.74 eV that are mainly due to intrinsic defects. Since the surfaces are Te-rich, the possible native defects must be Cd-vacancies, Te-interstitials or Te-in Cd sites. Clearly, in order to remove this mid-gap defect level, CdTe should be grown with Cd-richness. According to the results reported in ref [17], mid-gap defects at ~ 0.74 eV are completely removed for Cd-rich CdTe surfaces. Therefore, without any doubt, high-efficiency CdTe solar cells will be produced when Cd-rich CdTe or n-type CdTe is used in CdS/CdTe solar cells.

The literature also broadly reports the “grain boundary passivation” during CdCl₂ treatment. This needs deep investigations and understanding. Our preliminary thoughts were published before [27], and following is the summary of our current understanding of positive contributions from grain boundaries for the PV activity.

The secrets of CdCl₂ treatment and the involvement of grain boundaries after this treatment are the most interesting and need a deeper discussion. This needs consideration of both solid-state chemistry and physics principles. As reported in one of our publications [27], the melting point of pure CdTe crystal is 1092 °C. The reduction in the melting point of a material or a compound upon adding impurities is a well-established solid-state chemistry principle. During CdCl₂ treatment, the addition of numerous impurities on to the CdTe surface takes place. Some of these are namely excess Cd and Cl from CdCl₂, O from air annealing and also excess elemental Te deposited during growth. In addition to these, amorphous CdTe or crystallites of CdTe will be there in the grain boundaries. All the above impurities will drastically reduce the melting point of grain boundary materials to heat treatment temperature range of ~ 350–450 °C. Therefore, the grain boundary materials will melt into a liquid, while large CdTe crystals remain as solid material. This melting temperature has been identified as 385 ± 5 °C [27, 43] before, and suddenly the thin film becomes a collection of CdTe crystals floating on a thin film of liquid formed along grain boundaries. This is the main reason for the sudden collapse of the (111) XRD peak and appearance of other intense XRD peaks (220) and (311). The CdTe layers grown with (111) preferred orientation suddenly change due to floating of crystals in a liquid phase showing random nature of crystalline orientation, when heat treated and subsequently cooled down. After this process, most of the CdTe crystals extend across the thin film thickness showing columnar nature (Fig. 3a). During the heating, the liquid flows freely along grain boundaries due to convection currents and all elements mix up well, chemically react and excess elements could even evaporate from the liquid. Excess Cd from CdCl₂ and any elemental Te present can form CdTe compound [29] within grain boundaries and other elements present (Cl, O, etc.) dope this material to provide a certain electrical conductivity. Upon cooling, the CdTe crystals remain as solids, and the grain boundary material becomes a “melt-grown” material based on CdTe. To produce better solar cells, the grain boundary materials should solidify without forming any pinholes across the thin film. This certainly depends on the wetting properties of the composite material formed. Now, the two CdTe materials in crystals and in grain boundaries have different electrical conductivities and hence form lateral potential barriers as shown in Fig. 3b. This will happen with both n-type and p-type CdTe thin films and therefore establish lateral electric fields, E_t, along the crystal surfaces. Figure 3c shows the directions of E_t in the case of n-type CdTe thin films in addition to the main electric field of E_n across the solar cell. In this situation, photo-generated electron–hole (e–h) pairs are separated by two electric fields E_t and E_n. As a result, holes will mainly travel along the grain boundaries and electrons will travel in the opposite direction along the middle of CdTe crystals (see Fig. 3d). This motion has two advantages, minimising e–h annihilation and high mobility across the thin film normal to the TCO layer. Therefore, PV activity is enhanced with the positive contribution from grain boundaries. This is far beyond the grain boundary passivation and, in fact, enhancing the PV activity with the help of grain boundary activation effects. This type of PV activity will produce performance better than that of solar cells fabricated with epitaxial thin films. In this grain boundary activated situation, since photo-generated charge carriers are equal in number, the current densities along grain boundaries are much higher. The cross sections of grain boundaries surrounding the CdTe crystals are much smaller since they are simply “thin skin-like” boundaries. These high current densities along grain boundaries have been experimentally shown by two research groups using cross-sectional electron beam-induced current (EBIC) [44, 45], and one research group using Kelvin probe force microscopy (KPFM) [46].

With reference to the above discussion, it is now worth a comparison of two growth techniques: electrodeposition (ED) and close-space sublimation (CSS). ED is a low-temperature (< 100 °C) growth method, and CSS is a high-temperature (> 450 °C) growth technique. Therefore, the as-grown CdTe layers are very different; ED materials have grains in the nanoscale, and CSS materials have grown in µm scale. Therefore, the CdCl₂ treatment for these two materials shows some differences. According to the above discussion, CdCl₂ treatment provides two major changes: (i) formation of large crystals in the µm-scale covering the whole thickness of the film and (ii) the formation and/or enhancement of the transverse electric field (E_t) across grain boundaries. During CdCl₂ treatment of ED-CdTe, both these properties are introduced, and hence, the effect is drastic. However, in the case of CSS-CdTe, high-temperature grown materials have already formed large crystals in the µm-scale. Therefore, CdCl₂ treatment introduces or enhances the value of E_t showing a comparatively lower effect. But still there is a positive effect from the CdCl₂ treatment.

The above understanding on CdCl₂ treatment invokes revisiting of charge carrier mobility measurements in thin film CdTe solar cell material. Usual mobility measurements along the thin films (i.e. parallel to TCO surface) yield charge carrier mobilities parallel to TCO (µ_׀׀) and therefore subjected to a large number of grain boundary scattering (see Fig. 4). Therefore, these values can be very small due to the columnar nature of CdTe grains. However, during the PV action, photo-generated charge carriers move normal to the TCO (µ_┴) surface. In the case of large grains extending from CdS to the back contact, charge carriers mostly travel within one crystal and grain boundary scattering is minimum or non-existent. Similarly, the opposite carriers travel through the melt-grown grain boundary material approximately normal to the TCO surface. Therefore, µ_┴ could be much larger than usually measured µ_׀׀ values. This difference could be even several orders of magnitude, and hence, future research should focus on methods to determine µ_┴ rather than µ_׀׀ values. These new mobility values will help in accurate theoretical simulations to predict maximum possible efficiencies with grain boundary-enhanced PV effect in CdS/CdTe system.

The above discussion has been limited only to CdTe material and its solar cells. However, the observation of the large body of scientific publications on almost all polycrystalline PV materials shows columnar growth of these material layers. In particular, the low-temperature grown materials like CIGS, kesterites and perovskite materials show columnar growth and these columns extend throughout the device thickness. Therefore, the reported mobility values (µ_׀׀) should be much lower than the real mobility values (µ_┴) applicable when the device is operating. For the same reason, the theoretical calculations carried out with µ_׀׀ should be revisited using more realistic µ┴ values. Hence, the theoretical predictions for device efficiencies are expected to increase.

Chemical etching of mechanically polished n-CdTe wafers clearly showed that the top layers can be easily modified by using chemical etchants. Acidic solutions preferentially remove Cd-element and leave a Te-rich surface. On the other hand, alkaline solutions preferentially remove Te-element and leave a Cd-rich surface. This chemical nature is identical for thin films of CdTe, and native oxides like TeO₂ and CdTe_xO_y compounds are also usually found on these chemically etched surfaces.

The defect levels corresponding to these chemically etched CdTe surfaces have also been studied using PL measurements [17] (see Fig. 5). Five defect levels (E₁,…,E₅) have been identified as shown in Fig. 6, and E₁, E₂ and E₃ are dominant for Te-rich surfaces [47]. When the CdTe surfaces are produced with Cd-richness, E₁, E₂ and E₃ disappear and E₄ and E₅ become dominant defects (see Fig. 5a). These different properties obviously affect the properties of electrical contacts fabricated on them.

The presence of high concentrations of defects at experimentally observed defect levels seriously affects the n-CdTe/metal contacts formed on chemically etched surfaces (see Figs. 5a and 6). A large number of metal contacts fabricated on these surfaces show the Fermi level pinning at one of these defect levels. Pinning position depends on the history of materials and the nature of the chemically etched surface. Te-rich n-CdTe surfaces tend to pin the FL at E₁, E₂ or E₃ producing Schottky barriers (SB) with low-potential barrier heights (E_c–E₁) ~ 0.40 (E_c–E₂) ~ 0.65 or (E_c–E₃) ~ 0.73 eV. Cd-rich n-CdTe surfaces show FL pinning at E₄ or E₅ yielding high-potential barrier heights (E_c–E₄) ~ 0.96 or (E_c–E₅) ~ 1.18 eV. When one of the defects has high concentrations, the SB formed is independent of the metal or the electrical contact material used. If the material used for the electrical contact induces drastic interface interactions, the barrier height could change due to the removal of FL pinning. In order to produce excellent rectifying contacts on n-CdTe surfaces, Cd-rich CdTe surfaces should be used with un-reactive metals or electrical contact materials (see Fig. 5c). This FL pinning possibility introduces reproducibility issues for n-CdTe/metal interfaces. In summary, if large SBs with excellent rectifying contacts are desired, the n-CdTe surface should be prepared with Cd-richness and a non-reactive material like Sb or any other conducting material should be used (see Ref. [16]).

Without any doubt, the formation of p–n junction takes place if the CdTe layer is grown with p-type electrical conduction. Since the CdTe layer can easily exist in both conduction types, researchers must test its electrical conductivity during device development research without making any “assumptions”. Interpretation of the results highly depends on the device architecture. This is the main controversial issue in this field over the past few decades as most of the device outcomes have been always explained with simple p–n junction device architecture. Material studies of CdTe layers carried out by Shah et al. [48] using CSS growth showed that Te-rich CdTe results in p-type electrical conduction. But this research project is incomplete without testing Cd-rich CSS-CdTe. But to our knowledge, despite CSS being the most widely used technique, there is no published report on experimentally finding the electrical conduction type of CdTe layer used for CSS-grown PV device while explaining the device structure. If the material grown is indeed p-type, the CdS/CdTe hetero-junction is without doubt an n-p junction as shown in Fig. 7a, and the results can be interpreted and developed using this model.

If the CdTe layer is grown as n-type in electrical conduction due to variation in growth conditions, then the CdS/CdTe hetero-junction is an n–n-type weak rectifying contact. During the fabrication of metal contacts to n-CdTe, the FL pinning effects described as in Fig. 6 apply. To form a device with the highest slope or an intense internal electric field, the FL should be pinned at E₅ or forced to a place close to the VB maximum. In this situation, the device is an n–n + large SB at the back as shown in Fig. 7b. Now there are two rectifying interfaces: a weak rectifying junction at the n–n interface and a strong SB of ~ 1.18 eV at the back contact. These two junctions support each other adding currents, and therefore, the two junctions are connected in parallel. Since the SB is extremely large, even exceeding the potential barrier of CdTe p–n junction, and the whole device has a two-junction architecture, this device can perform better than the simple p–n junction. But unfortunately, optimisation of the device parameters by trial-and-error method, forming an n–n + SB device and then attempting to interpret the results using a simple p–n junction based on popular assumption, has been a real confusion in this field for several decades.

In order to experimentally test the situation, we have grown a series of CdTe layers covering p-CdTe, i-CdTe and n-CdTe ranges as shown in Fig. 1. These layers have been treated in the same way, and devices were fabricated with the same electrical contact material. The device parameters, V_oc, J_sc, FF and η have been investigated in two recent series of experiments [49, 50]. Figure 8 shows the latest set of results [50], and both p-CdTe and n-CdTe layers produce PV active devices, but the high performance comes from n-CdTe layers. This experiment has been repeated, and the results are consistent [49, 50]. Therefore, the highest performing devices arise from n-CdTe layers, and the device architecture is n–n + SB for high-efficiency devices.

The device architecture shown in Fig. 7b was first published in 2002 [19] for high-performing CdS/CdTe solar cells, and the CdTe used in this device is reported as an n-type material. Soon after, in 2003, Jaegermann’s group reported [51] a surprising result of n-CdTe solar cells producing highest efficiencies. Their comprehensive work on surfaces and interfaces investigated the CdS/CdTe solar cell efficiency as a function of the position of the Fermi level in CdTe. They obtained highest efficiencies with n-type CdTe and reported “This surprising result does not correspond to the accepted model of the device physics of the CdS/CdTe solar cell,” i.e. the p–n junction model. More recently in 2013 [52] and 2015 [53], comprehensive works on both theoretical and experimental work by NREL group reported that Cd-rich CdTe surfaces are more suitable for solar cell fabrication. Clearly, the Cd-rich CdTe material is n-type in electrical conduction, and therefore, the device architecture shown in Fig. 7b is more appropriate to describe the highest efficient CdS/CdTe solar cells.

Impurity PV effect can be used by devices as shown in Fig. 9. These have large bandgap in the front, and bandgap value gradually reduces towards the rear of the device. In order to keep large V_oc values above 1.00 V, the smallest bandgap should be limited to ~ 1.40 eV. Then, the photons with energy less than the smallest bandgap used can be absorbed utilising native defects via multi-step absorption process or impurity PV effect. This is shown in Fig. 9, and this process can be used to absorb almost all photons available in the solar spectrum.

In addition, the heat from the surrounding can also contribute to the multi-step absorption process providing another input of photons to this kind of devices. All these processes contribute to the increase in J_sc, when the right conditions exist in this type of devices. When the multi-step absorption process is dominant, the recombination process is suppressed in such devices.

In the type of devices shown in Fig. 9, the probability of impact ionisation also increases and takes place via two different mechanisms. The photo-generated electrons in the front of the device accelerate towards the back contact and travel through smaller bandgap materials. When the electron achieves kinetic energy greater than the bandgap of the absorbing material, an additional e–h pair is created by band-to-band transition (see Fig. 9).

The second type of impact ionisation is more attractive and highly possible. Towards the rear of the devices, native defects are filled by infrared (I-R) photons coming from both the solar spectrum and the surroundings. The accelerating photo-generated electrons from the front will have enough energy to transfer trapped electrons from defect levels to the conduction band. This combined process of impurity PV effect and impact ionisation has a high probability of creating more charge carriers, and this will be an avalanche effect. Since both impurity PV effect and impact ionisation are built into this device, and with an additional input from the surrounding I-R radiation, the J_sc can achieve very high values beyond ~ 26 mA cm⁻² for CdTe solar cells. There are many publications with high J_sc values, and First Solar has also reported 31.69 mA cm⁻² for CdS/CdTe solar cells [57] which is certainly exceeding 26 mA cm⁻².