Low power and high speed design issues of CMOS  Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS) technology. Average power consumption and input to output gate delay for both Hamming code generation and error detection circuit are analyzed at 22 nm and 16 nm channel length of Metal Oxide Semiconductor (MOS) transistor. The functionality of the circuits are clarified using Tanner SPICE (T-SPICE) software. The average power consumption and input to output gate delay of the circuits are reported considering the parameters—power supply voltage, channel width to length ratio of transistors. It has been observed that whenever power supply voltage (V_DD) increases, power consumption across the circuits increases, however gate delay decreases for both the circuit for fixed channel width to length ratio of the transistors. On the other hand, for fixed value of V_DD if channel width to length ratio of NMOS transistor increases gate delay decreases however average power consumption increases. The variation of average power consumption and delay has also been reported with respect to K_PN ratio. K_PN is the ratio of channel width to length ratio of PMOS transistor to channel width to length ratio of NMOS transistor. Average power consumption is more for higher value of K_PN ratio. In contrast gate delay is less at higher value K_PN ratio. In this work, the values of average power consumption and gate delay are of the order of microwatt and picosecond respectively. The average power consumption of the Hamming code generation circuit in this work at 0.8 V of V_DD is 0.2 µW and 1.3 µW for 22 nm and 16 nm cannel length of MOS transistor respectively. Whereas at the V_DD of 0.8 V, the average power consumption of the error detection circuit is 0.4 µW and 2.3 µW respectively for 22 nm and 16 nm cannel length. The gate delay of the Hamming code generation circuit in this work at V_DD of 0.8 V is 4.7 ps and 3.3 ps for for 22 nm and 16 nm cannel length of MOS transistor respectively. Also at the V_DD of 0.8 V, the gate delay of the error detection circuit has been reported in this work is 16.4 ps and 12.5 ps for 22 nm and 16 nm channel length respectively. Therefore for low power and high speed Very Large Scale Integrated (VLSI) circuit design this work is applicable.