Memristor-Based Nanoelectronic Computing Circuits and Architectures

The memristor is considered one of the most promising nano-devices among those currently being studied for possible use in electronic systems of the future. The best performance features which have been demonstrated in published experimental results regarding research device prototypes so far include fast switching speed, high endurance and data retention, low power consumption, high integration density, and (perhaps most importantly) CMOS compatibility. Undoubtedly, the combination of such advantageous characteristics in a single device justifies the phenomenal research interest that resistance-switching devices have generally attracted over the last few years and verify the existing rumors about their potential application in both storage and processing units of future electronic systems. Memristive nano-devices are the focus of this book and this chapter aims to introduce the reader to their fundamental properties on which the presented study is based.

Amongst several emergent applications of the memristance switching phenomenon, the implementation of logic circuits is gaining considerable attention. Memristor-based logic circuits open new pathways for the exploration of advanced computing architectures as promising alternatives to conventional integrated circuit technologies. However, up to now no standard logic design methodology exists, since it is not immediately clear what kind of computing architectures would in practice benefit the most from the computing capabilities of memristors. This chapter addresses memristive logic circuit design and computational methodologies, aiming to approach this novel area of research while motivating for further research on innovative design strategies, which comply with emerging technologies. First, a summary of the most recognized memristive logic circuit design concepts is provided. Then two novel logic design paradigms are presented, which aim to address several drawbacks of other existing design concepts in the literature, and to facilitate the incorporation of memristors in currently established logic circuit architectures. Thus they could be promising candidates to be used in future electronic systems design. The proposed design paradigms are validated through SPICE-based simulations for a variety of complex combinational logic circuits.

Among several types of emerging memory technologies, memristor-based nonvolatile resistive RAM (ReRAM) is currently being investigated as a promising candidate to potentially replace the popular Flash memories, and even other conventional memories such as SRAM and DRAM. At the architectural level, crossbar cell array structure is considered one of the best ways to implement memristor-based ReRAM. This chapter presents an overview of promising ReRAM technologies, their potential benefits, and the key research challenges, with a focus on reduction/oxidation (Redox)-based RAM. It briefly describes the basic operation principles of memristive memory cells, and presents the memristor-based crossbar memory architecture to finally focus on the serious negative impact of the current sneak-paths. Then, two possible methodologies are explored as means to deal with the sneak-path problem, concerning (i) novel storage cell structures, and (ii) modifications in the memory architecture. More specifically, (i) anti-parallel memristive switches are studied as potential cross-point elements in ReRAM arrays, in comparison with anti-serial (complementary) memristive switches. A comprehensive and comparative presentation between them is provided, while commenting on their overall performance and the most appropriate switching characteristics that the structural memristors should have, in order to better fit to memory applications. Moreover, (ii) five alternative architectures (topologies) for passive crossbar ReRAM are presented, which are based on the introduction of a certain percentage of insulating nodes spread out inside the array according to specific distribution patterns. Both approaches enable crossbar memory arrays without select devices, thus they simplify the array fabrication process and could be well-suited for future data storage applications. Finally, XbarSim, a GUI-based educational simulation tool aiming to serve students/researchers who wish to explore and study the memristive crossbar circuit architecture, is presented.

Memristors demonstrate a natural basis for computation that combines information processing and storage in the memory itself. A very powerful and promising memristor-based computing structure, which implements analog parallel computations, is the memristor network. In such structure there is continuous information exchange during calculations which renders a tremendous increase of computational power due to the massively parallel network dynamics. In this chapter we explore this computing concept via numerical and circuit simulations for the purpose of investigating the network dynamics, utilizing the well-documented physics of single devices and known network topologies. We address two of the probably most well-known inherently complex problems, in terms of computation time, i.e. the shortest path and the maze-solving problems, via computations in memristor networks. For these specific problems we further extend already proposed memristor network-based computing approaches by introducing certain modifications in the computing platform. Several scenarios are examined considering also the inclusion of devices with different switching characteristics in the same computation. Additionally, we address the appropriate mapping issue of graph-based computational problems via a novel modeling approach, which is based on specific circuit models describing several types of edges connecting the graph vertices. The emergence of new functionalities opens doors to exciting new computing concepts and encourages the development of parallel memristive computing systems.