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Journal of Electronic Testing

Erschienen in:

03.05.2021

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

verfasst von: Muhammad Sheikh Sadi, Sumaiya Sumaiya, Mouly Dewan, Atikur Rahman

Erschienen in: Journal of Electronic Testing | Ausgabe 2/2021

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Abstract

A new error detection and correction methodology, defined as Horizontal-Vertical-Diagonal-N-Queen-Parity (HVDNQ), is proposed in this paper. This approach relies on five different types of parities: horizontal parity, vertical parity, forward diagonal parity, backward diagonal parity, and queen parity. This method works on an N X N cell area and can correct multi-bit upsets. The experimental analysis validates the effectiveness of the proposed methodology by comparing its efficiency with existing methodologies. In different varieties of error patterns such as equilateral triangle, pentagon, hexagon etc., the capability of error detection and correction of HVDNQ is much better than existing methods.

Vorheriger Artikel Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit

Nächster Artikel Radiation Tolerant SRAM Cell Design in 65nm Technology

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Titel: Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity
verfasst von: Muhammad Sheikh Sadi
Sumaiya Sumaiya
Mouly Dewan
Atikur Rahman
Publikationsdatum: 03.05.2021
Verlag: Springer US
Erschienen in: Journal of Electronic Testing / Ausgabe 2/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI: https://doi.org/10.1007/s10836-021-05942-4

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