An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic

High computational complexity of multimedia applications on the portable devices demands a high speed and energy efficient processing cores. The performance of arithmetic unit within these cores significantly affects the overall performance of the devices. Therefore, this paper presents carry look ahead (CLA) adder based two efficient accuracy reconfigurable (AR) adder designs namely AR-CLA-I and AR-CLA-II. The AR-CLA-I design is developed using 4-bit CLA segments with novel approximate sum generation approach. Whereas, the AR-CLA-II design is developed using a novel complementary logic based CLA segment which utilizes proposed new logic formulation. The proposed AR-CLA designs can be reconfigured to achieve high energy-efficiency at cost of acceptable loss in quality. The synthesis results on TSMC 65nm CMOS technology library show that the proposed AR-CLA-I (AR-CLA-II) provides on average 76.52% (80.62%) and 71.65% (74.16%) less area and energy respectively over the best available CLA based approximate adder. The quality metrics of the proposed AR-CLA adder designs as standalone unit demonstrates significant improvement over the existing approximate adder designs. Finally, Sobel edge detectors (SED) embedded with proposed AR-CLA adders provide 71.89 dB higher PSNR over SED embedded with best known approximate adder.