Non-logic Devices in Logic Processes

In this chapter, we provide a brief introduction and review the importance of semiconductor devices in supporting the whole electronics industry, the economics of semiconductor industry, the Moore’s law, and a number of corollaries that may be used to derive the best practices in designing devices for use in integrated circuits.

In this chapter, we provide a brief review of basic CMOS devices and device physics. We start by walking through the basic devices that are available in generic CMOS processes, covering rudimentary device physics that are of particular interests to the central theme of this book (including p–n junctions and gate oxide breakdown) and their effects on the design rules of non-logic active and passive devices. As power consumption has become the main barrier for IC design and applications, for example, in wearable ICs, it is useful to always keep in mind the fundamental factors affecting CMOS power consumption. We conclude with a brief analysis of power consumption of CMOS ICs.

In this chapter, we review the process steps of a generic, planar logic CMOS process. The fabrication of I/O devices, which has a different gate oxide from that of the core devices, is shown in parallel with the core devices. We also discussed the fabrication of native devices and potential use of spacer for charge storage—two features that will see use in later chapters. The basics of mask design, process monitoring, and wafer fabrication economics are then reviewed to highlight the best practices discussed in Chap. 2, i.e., the advantages and trade-offs to use the simplest and basic CMOS process.

This is a core chapter for this book, covering the design of nonstandard MOSFETs using logic CMOS processes. In Sect. 4.2 we discussed the design of several types of MOSFETs that have different threshold voltages than those provided by the foundries. In particular, the bandgap-engineered FETs have found wide use in voltage reference circuits. Then in Sect. 4.3 we discuss another important class of MOSFETs—LDMOS that can operate at voltage over 15 V and can be manufactured in a generic CMOS process without any process modification. Design, reliability, and manufacturability of LDMOS are reviewed.

In this chapter, we discuss another important class of devices, devices containing floating gate including floating-gate transistors and capacitors, that can be produced in logic CMOS processes. We describe some examples of making floating-gate memory cells in a logic process and several methods of programming, including tunneling and hot carrier injection, floating-gate devices. The importance of coupling ratio and its implications to the NVM cell design is discussed extensively. In the last section, we review a semi-floating-gate device, that of gain cell which have found application as an embedded DRAM cell.

In this short chapter, we review bipolar junction transistors (BJTs) that can be obtained in the basic CMOS processes. The parasitic BJTs have been extensively discussed, mostly in the context of avoiding the latch-up risk for CMOS ICs. We here focus on a couple of applications, especially in the voltage reference circuits, of the BJTs. We also discuss a special punchthrough transistor that can be obtained from the CMOS process.

In this chapter, we discuss special diodes that can be made in standard logic CMOS processes. We first discuss the polysilicon diode and a close relative, the polysilicon resistor. In particular, the different temperature coefficients of resistivity (TCR) of p and n polysilicon make it possible to obtain a resistor that is temperature independent. Then we showed several examples of making Schottky diodes in logic processes and discussed their properties and applications.

Chapter 8 is the first of three chapters that form a core application for the devices we discussed in Part II, in embedded NVMs. In this chapter, we give an overview of the embedded NVM design using logic CMOS process. We review the basic memory cell design, the programming and erasing methods, and array structure of embedded NVMs. High-voltage circuits, including charge pumps and high-voltage switches, are also discussed. Reliability issues associated with embedded NVMs are introduced.

In this chapter, we focus on the One-Time Programmable (OTP) embedded NVM using basic logic CMOS processes. We review poly fuse, antifuse, and floating-gate-based OTP memory cell and arrays.

In this chapter, we focus on the Multiple-Times Programmable (MTP) embedded NVM using basic logic CMOS processes. Several types of floating-gate-based NVMs are discussed, including medium density eNVM based on two-transistor (2T) memory cell, and low density but also low-power three-transistor (3T) memory cell. In the last section, we review the charge trapping-based NVM cell design.

In this chapter, we describe several non-data-storage applications of the floating-gate memory made in the logic process. We first review digital-to-analog converters that use floating-gate transistors as analog storage for trimming of current sources. Adaptive floating-gate comparator and several applications are briefly described. RFID systems application is then reviewed where many of the novel devices and circuits, including native devices, bandgap-engineered device, and logic NVMs, played a critical role and enabled low cost and low power RFID chips. Use of floating-gate transistor in neutral networks is then discussed. The use of floating-gate devices for multi-input tunable biosensors will be discussed in Chap. 12, while the transmission line-based waveform-shaping structures in the logic process will be investigated in Chap. 13.

We will start from the general requirements in chemical and biosensors and then narrow down the specific advantages of CMOS implementation in view of signal transduction from the biological to the electronic domains. As the amperometric sensing on CMOS is similar to most popular mixed-signal designs, we will only focus on field-effect sensors with a polarizable electrode or interface. A general device based on the neuromorphic principles in the previous chapters will be presented for its structure, operation, and circuit models. Variations in device implementation will be examined under the unified neuromorphic circuit model. The interface between the electrode and the buffer media will be modeled with an electrical network. We then present sample measurements in different buffer media and examine the current difficulties in realistic operations with long-term reliability. We will conclude at future challenges and outlook for the biological interface to the CMOS world.

Most of the CMOS mixed-signal circuits, including digital, analog, and RF applications, have layout sizes much smaller than the wavelength of design interest (or equivalently the operating frequency is much lower than the speed of light divided by the layout size), and are hence treated as lumped circuit elements or scattering blocks in conventional microwave circuits. These lumped circuits do not need to consider the coupling between the electric and magnetic fields governed by the Maxwell equations, but only the electrostatic Poisson equation with the displacement current would be sufficient. On the other hand, this chapter will introduce how to design distributive circuit structures in logic CMOS processes. Distributive circuits means the physical size of the component under consideration is comparable to the wavelength of interest, the electrostatic picture is insufficient, and the electromagnetic wave propagation needs to be considered for the module characteristics. As wave propagation is part of the design considerations, we will investigate the waveform shaping characteristics for these distributive modules, whether the shaping is a desirable feature or an unwanted distortion. As there are many excellent texts on the CMOS RF circuit modules such as on-chip inductors and resonators, we will focus only on distributive structures such as on-chip waveguides and transmission lines. We will then illustrate the design and characteristics of both semidiscrete and lumped-element transmission lines, together with varactor loading to make functionalities available in nonlinear transmission lines (NLTL). We will finally investigate the layout dependence of line folding and floating-metal isolation structures in practical waveguide and transmission line structures.

We conclude this book by looking at the potential directions that IC industry is going to continue the Moore’s law scaling and the associated impacts to the non-logic devices discussed in previous chapters. We first review the fundamental limits to the continued IC scaling, including those implied by the quantum mechanics and quantum information theory. As we close to those fundamental limits, two main directions that IC industry is moving toward include the use of the vertical dimension and new materials to build new ICs. The later approach has resulted in the development of many emerging memory technologies, including STT-RAM, PCRAM, and RRAM. Both directions could open up new opportunities for designing new non-logic devices. Finally new computing paradigms, including quantum computing, may usher in fundamentally new processes for building these new computing devices.