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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 1/2017

29.11.2016

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

verfasst von: Shiromani Balmukund Rahi, Pranav Asthana, Shoubhik Gupta

Erschienen in: Journal of Computational Electronics | Ausgabe 1/2017

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Abstract

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.
Vorheriger Artikel Group III–V ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors
Nächster Artikel Double aperture double-gate vertical high-electron-mobility transistor

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Metadaten
Titel
Heterogate junctionless tunnel field-effect transistor: future of low-power devices
verfasst von
Shiromani Balmukund Rahi
Pranav Asthana
Shoubhik Gupta
Publikationsdatum
29.11.2016
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 1/2017
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0936-9

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