Junctionless double gate non-parabolic variable barrier height Si-MOSFET for energy efficient application

Analytical model for the computation of drain current of the junction-less double gate junction-less MOSFET with a variable barrier height has been presented in this paper. Band non-parabolicity is also assumed to increase the efficacy of the proposed model, applicable for the ultrathin nano-devices. Variable barrier height uses intra band tunnelling to enhance the I_ON/I_OFF by reducing the off current of the device significantly. Also low sub-threshold slope can be achieved using this proposed device structure for high switching applications. Besides ten stages Inverter has been implemented using the proposed device to study the impact of constrictions on power dissipations and delay. The proposed models have been validated by the extensive simulations using SILVACO TCAD. Simulation shows that the proposed data is matched with the simulated data with high accuracy.