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Microsystem Technologies
Erschienen in: Microsystem Technologies 12/2017

08.09.2017 | Technical Paper

Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology

verfasst von: Muhammad Imran Khan, Affaq Qamar, Faisal Shabbir, Rizwan Shoukat

Erschienen in: Microsystem Technologies | Ausgabe 12/2017

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Abstract

This research paper focuses on the design, development and implementation of a pipelined analog to digital (A/D) converter of 8 bits with sampling rate of 25 MHz in 350 nm CMOS process technology. The architecture utilizes the digital correction for each stage based on a 1.5 bit per stage structure. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200 MHz ft is used for sampling and amplification in each stage. Differential dynamic comparators are used to implement the decision levels required for the 1.5 bit per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full adders. Finally, the paper describes the floorplan and layout of design.
Vorheriger Artikel Parametric modeling of a novel longitudinal vibration-based energy harvester using magneto-electro-elastic materials
Nächster Artikel Transient behavior and dynamic pull-in instability of electrostatically-actuated fluid-conveying microbeams

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Literatur
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Metadaten
Titel
Design, development and implementation of a low power and high speed pipeline A/D converter in submicron CMOS technology
verfasst von
Muhammad Imran Khan
Affaq Qamar
Faisal Shabbir
Rizwan Shoukat
Publikationsdatum
08.09.2017
Verlag
Springer Berlin Heidelberg
Erschienen in
Microsystem Technologies / Ausgabe 12/2017
Print ISSN: 0946-7076
Elektronische ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-017-3550-2

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