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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 1/2017

19.12.2016

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Erschienen in: Journal of Computational Electronics | Ausgabe 1/2017

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Abstract

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.
Vorheriger Artikel Double aperture double-gate vertical high-electron-mobility transistor
Nächster Artikel Quantum analysis based extraction of frequency dependent intrinsic and extrinsic parameters for GEWE-SiNW MOSFET

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Literatur
1.
Colinge, J.P., Gao, M.H., Romano-Rodríguez, A., Maes, H., Claeys, C.: Silicon-on-insulator “gate-all-around device”. In: Proceedings of the IEEE Technical Digest IEDM, pp. 595–598. IEEE (1990)
2.
Ferain, I., Colinge, C.A., Colinge, J.P.: Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature 479, 310–316 (2011)CrossRef
3.
Nayak, K., Bajaj, M., Konar, A., Oldiges, P.J., Natori, K., Iwai, H., Murali, K.V.R.M., Rao, V.R.: CMOS logic device and circuit performance of Si gate all around nanowire MOSFET. IEEE Trans. Electron Devices 61(9), 3066–3074 (2014)CrossRef
4.
Hashemi, P., Gomez, L., Hoyt, J.L.: Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter. IEEE Electron Device Lett. 30(4), 401–403 (2009)CrossRef
5.
Hashemi, P., Gomez, L., Canonico, M., Hoyt, J.L.: Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs. In: Proceedings of the Electron Devices Meeting, IEDM, pp. 1–4. IEEE (2008)
6.
Nguyen, V.-H., Triozon, F., Niquet, Y.-M.: Strain effects on transport properties of Si nanowire devices. In: Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices, pp. 89–92. IEEE (2013)
7.
Luong, G.V., Knoll, L., Blaeser, S., Süess, M.J., Sigg, H., Schäfer, A., Trellenkamp, S., Bourdelle, K.K., Buca, D., Zhao, Q.T., Mantl, S.: Demonstration of higher electron mobility in Si nanowire MOSFETs by increasing the strain beyond 1.3%. Solid State Electron. 108, 19–23 (2015)CrossRef
8.
Rim, K., Hoyt, J.L., Gibbons, J.F.: Fabrication and analysis of deep submicron strained-Si N-MOSFET’s. IEEE Trans. Electron Devices 47(7), 1406–1415 (2000)CrossRef
9.
Dalapati, G.K., Chattopadhyay, S., Driscoll, L.S., O’Neill, A.G., Kwa, K.S.K., Olsen, S.H.: Extraction of strained-Si metal-oxide-semiconductor field-effect transistor parameters using small signal channel conductance method. J. Appl. Phys. 99(3), 034501 (2006)CrossRef
10.
Biswas, A., Bhattacherjee, S.: Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate. Microelectron. Reliab. 54, 1527–1533 (2014)CrossRef
11.
Liu, Y., Li, Z.: An analytical threshold voltage model of strained surrounding-gate MOSFETs. In: Proceedings of the IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp. 1–3. IEEE (2012)
12.
Singh, T.V., Kumar, M.J.: Effect of the Ge mole fraction on the formation of a conduction path in cylindrical strained-silicon-on-SiGe MOSFETs. Superlattices Microstruct. 44, 79–85 (2008)CrossRef
13.
Chao, P.-J., Li, Y.: Impact of geometry aspect ratio on 10-nm gate-all-around silicon-germanium nanowire field effect transistors. In: Proceedings of the 14th IEEE International Conference on Nanotechnology, pp. 452–455. IEEE (2014)
14.
Li, M., Yeo, K.H., Yeoh, Y.Y., Suk, S.D., Cho, K.H., Kim, D.-W., Park, D., Lee, W.-S.: Experimental investigation on superior PMOS performance of uniaxial strained \(<\)110\(>\) silicon nanowire channel by embedded SiGe source/drain. In: Proceedings of the Electron Devices Meeting, IEDM, pp. 899–902. IEEE (2007)
15.
Zhang, Y., Li, Z., Wang, C., Liang, F.: Compact analytical threshold voltage model of strained gate-all-around MOSFET fabricated on Si\(_{1-x}\)Ge\(_{x}\) virtual substrate. IEICE Trans. Electron. 99(2), 302–307 (2016)CrossRef
16.
Liow, T.-Y., Tan, K.-M., Lee, R.T.P., Zhu, M., Tan, B.L.-H., Balasubramanian, N., Yeo, Y.-C.: Strained silicon nanowire transistors with germanium source and drain stressors. IEEE Trans. Electron Devices 55(11), 3048–3055 (2008)CrossRef
17.
Liow, T.-Y., Tan, K.-M., Lee, R.T.P., Zhu, M., Tan, B.L.-H., Balasubramanian, N., Yeo, Y.-C.: Germanium source and drain stressors for ultrathin-body and nanowire field-effect transistors. IEEE Electron Device Lett. 29(7), 808–810 (2008)CrossRef
18.
Liu, B., Wong, H.-S., Yang, M., Yeo, Y.-C.: Strained silicon nanowire p-channel FETs with diamond-like carbon liner stressor. IEEE Electron Device Lett. 31(12), 1371–1373 (2010)CrossRef
19.
Roldán, J.B., Gamiz, F., Jiménez-Molinos, F., Sampedro, C., Godoy, A., Ruiz, F.J.G., Rodriguez, N.: An analytical \(I{-}V\) model for surrounding-gate transistors that includes quantum and velocity overshoot effects. IEEE Trans. Electron Devices 57(11), 2925–2933 (2010)CrossRef
20.
Lázaro, A., Iñíguez, B.: RF and noise model of gate-all-around MOSFETs. Semicond. Sci. Technol. 23(7), 075022 (2008)CrossRef
21.
Smaani, B., Latreche, S., Iñíguez, B.: Compact drain-current model for undoped cylindrical surrounding-gate metal-oxide-semiconductor field effect transistors including short channel effects. J. Appl. Phys. 114(22), 224507 (2013)CrossRef
22.
Tsormpatzoglou, A., Tassis, D.H., Dimitriadis, C.A., Ghibaudo, G., Pananakakis, G., Clerc, R.: A compact drain current model of short-channel cylindrical gate-all-around MOSFETs. Semicond. Sci. Technol. 24(7), 075017 (2009)CrossRef
23.
Campbell, J.P., Cheung, K.P., Suehle, J.S., Oates, A.: A simple series resistance extraction methodology for advanced CMOS devices. IEEE Electron Device Lett. 32(8), 1047–1049 (2011)CrossRef
24.
Kumar, S., Kumari, A., Das, M.K.: Development of a simulator for analyzing some performance parameters of nanoscale strained silicon MOSFET-based CMOS inverters. Microelectron. J. 55, 8–18 (2016)CrossRef
25.
Tanner Tools User’s Manual, Tanner Research Inc. (2006)
26.
PSPICE User’s Manual, Cadence ORCAD 16.6, Cadence Design Systems, Inc., San Jose, CA, USA (2012)
27.
Atlas User’s Manual: Device simulation software. Santa Clara, Silvaco International (2012)
28.
Medici User’s Manual: Two dimensional device simulation program. Synopsys Inc., Sunnyvale, CA, USA (2012)
29.
Pourfath, M., Sverdlov, V., Selberherr, S.: Transport modeling for nanoscale semiconductor devices. In: Proceedings of the 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1737–1740. IEEE (2010)
30.
Evans, G.A., Blackledge, J.M., Yardley, P.D.: Numerical Methods for Partial Differential Equations. Springer, London (2000)CrossRefMATH
31.
Kumar, G., Singh, M., Trivedi, G., Bulusu, A.: A parallel device simulator based on finite element method. In: Proceedings of the International Conference on Computational Science and Computational Intelligence, pp. 30–35. IEEE (2015)
32.
Xie, Q., Xu, J., Taur, Y.: Review and critique of analytic models of MOSFET short-channel effects in subthreshold. IEEE Trans. Electron Devices 59(6), 1569–1579 (2012)CrossRef
33.
Narimani, K., Luong, G.V., Schulte-Braucks, C., Trellenkamp, S., Zhao, Q.T., Mantl, S., Chowdhury, M.F.: Current mirrors with strained Si single nanowire gate all around Schottky barrier MOSFETs. In: Proceedings of the Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp. 178–181. IEEE (2016)
34.
Dillen, D.C., Wen, F., Kim, K., Tutuc, E.: Coherently strained Si-Si\(_{x}\)Ge\(_{1-x}\) core-shell nanowire heterostructures. Nano Lett. 16, 392–398 (2016)CrossRef
35.
Mei, G., Li, P., Hu, G., Liu, R., Wang, L., Tang, T.: Quantum mechanical effects on the threshold voltage of surrounding-gate MOSFETs. Microelectron. J. 43, 894–897 (2012)CrossRef
36.
Li, Y., Hwang, C.-H.: The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding-gate field-effect transistor and circuit. Semicond. Sci. Technol. 24(9), 095018 (2009)CrossRef
37.
Kumar, S., Jha, S.: Impact of elliptical cross-section on the propagation delay of multi-channel gate-all-around MOSFET based inverters. Microelectron. J. 44, 844–851 (2013)CrossRef
38.
Hashemi, P.: Gate-all-around silicon nanowire MOSFETs: top-down fabrication and transport enhancement techniques. Ph.D. dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA (2010)
39.
Suk, S.D., Lee, S.-Y., Kim, S.-M., Yoon, E.-J., Kim, M.-S., Li, M., Oh, C.W., Yeo, K.H., Kim, S.H., Shin, D.-S., Lee, K.-H., Park, H.S., Han, J.N., Park, C.J., Park, J.-B., Kim, D.-W., Park, D., Ryu, B.-I.: High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability. In: Proceedings of the IEEE Technical Digest IEDM, pp. 717–720. IEEE (2005)
40.
Zhai, Y., Mathew, L., Rao, R., Palard, M., Chopra, S., Ekerdt, J.G., Register, L.F., Banerjee, S.K.: High-performance vertical gate-all-around silicon nanowire FET with high-\(k\)/metal gate. IEEE Trans. Electron Devices 61(11), 3896–3900 (2014)CrossRef
41.
Pratap, Y., Ghosh, P., Haldar, S., Gupta, R.S., Gupta, M.: An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering. Microelectron. J. 45, 408–415 (2014)CrossRef
42.
Fashtami, T.N., Ali, S.Z.S.: Performance investigation of gate-all-around nanowire FETs for logic applications. Indian J. Sci. Technol. 8(3), 231–236 (2015)CrossRef
43.
Davis, A.T.: Implicit mixed-mode simulation of VLSI circuits. Ph.D. dissertation, Department of Electrical Engineering, University of Rochester, Rochester, New York (1991)
44.
Lee, C.-C., Cheng, H.-C., Hsu, H.-W., Chen, Z.-H., Teng, H.-H., Liu, C.-H.: Mechanical property effects of Si\(_{1-x}\)Ge\(_{x}\) channel and stressed contact etching stop layer on nano-scaled n-type metal-oxide-semiconductor field effect transistors. Thin Solid Films 557, 316–322 (2014)CrossRef
45.
Roldán, J.B., Gámiz, F., López-Villanueva, J.A., Carceller, J.E.: A monte carlo study on the electron-transport properties of high-performance strained-Si on relaxed Si\(_{1-x}\)Ge\(_{x}\) channel MOSFETs. J. Appl. Phys. 80(9), 5121–5128 (1996)CrossRef
46.
Auth, C.P., Plummer, J.D.: Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET’s. IEEE Electron Device Lett. 18(2), 74–76 (1997)CrossRef
47.
Young, K.K.: Analysis of conduction in fully depleted SOI MOSFET’s. IEEE Trans. Electron Devices 36(3), 504–506 (1989)CrossRef
48.
Kumar, M.J., Venkataraman, V., Nawal, S.: Impact of strain or Ge content on the threshold voltage of nanoscale strained-Si/SiGe bulk MOSFETs. IEEE Trans. Device Mater. Reliab. 7(1), 181–187 (2007)CrossRef
49.
Zhang, L., Li, L., He, J., Chan, M.: Modeling short-channel effect of elliptical gate-all-around MOSFET by effective radius. IEEE Electron Device Lett. 32(9), 1188–1190 (2011)CrossRef
50.
Arora, N.: MOSFET Modeling for VLSI Simulation—Theory and Practice. World Scientific, Singapore (2007)CrossRef
51.
Duarte, J.P., Choi, S.-J., Moon, D.-I., Ahn, J.-H., Kim, J.-Y., Kim, S., Choi, Y.-K.: A universal core model for multiple-gate field-effect transistors. Part I: Charge model. IEEE Trans. Electron Devices 60(2), 840–847 (2013)CrossRef
52.
Tienda-Luna, I.M., Ruiz, F.J.G., Donetti, L., Godoy, A., Gámiz, F.: Modeling the equivalent oxide thickness of surrounding gate SOI devices with high-\(k\) insulators. Solid State Electron. 52, 1854–1860 (2008)CrossRef
53.
Kang, T.-K.: Evidence for silicon bandgap narrowing in uniaxially strained MOSFETs subjected to tensile and compressive stress. IEEE Electron Device Lett. 33(6), 770–772 (2012)CrossRef
54.
Batwani, H., Gaur, M., Kumar, M.J.: Analytical drain current model for nanoscale strained-Si/SiGe MOSFETs. Int. J. Computat. Math. Elect. Electron. Eng. 28(2), 353–371 (2009)CrossRefMATH
55.
Gaubert, P., Teramoto, A., Ohmi, T.: Modelling of the hole mobility in p-channel MOS transistors fabricated on (110) oriented silicon wafers. Solid State Electron. 54, 420–426 (2010)CrossRef
56.
Fleury, D., Cros, A., Brut, H., Ghibaudo, G.: New \(Y\)-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs. In: Proceedings of the IEEE International Conference on Microelectronic Test Structures, pp. 160–165. IEEE (2008)
57.
Kim, Y.-R., Lee, S.-H., Sohn, C.-W., Choi, D.-Y., Sagong, H.-C., Kim, S., Jeong, E.-Y., Kim, D.-W., Hong, H., Baek, C.-K., Lee, J.-S., Jeong, Y.-H.: Simple S/D series resistance extraction method optimized for nanowire FETs. IEEE Electron Device Lett. 34(7), 828–830 (2013)CrossRef
Metadaten
Titel
Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications
Publikationsdatum
19.12.2016
Erschienen in
Journal of Computational Electronics / Ausgabe 1/2017
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0941-z

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