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Über dieses Buch

This book provides a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modelling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device-level, cell-level, circuit-level, architectural-level, software level and system level soft error mitigation techniques.

The book contains a comprehensive presentation of most recent advances on understanding, qualifying and mitigating the soft error effect in advanced electronic systems, presented by academia and industry experts in reliability, fault tolerance, EDA, processor, SoC and system design, and in particular, experts from industries that have faced the soft error impact in terms of product reliability and related business issues and were in the forefront of the countermeasures taken by these companies at multiple levels in order to mitigate the soft error effects at a cost acceptable for commercial products. In a fast moving field, where the impact on ground level electronics is very recent and its severity is steadily increasing at each new process node, impacting one after another various industry sectors (as an example, the Automotive Electronics Council comes to publish qualification requirements on soft errors), research and technology developments and industrial practices have evolve very fast, outdating the most recent books edited at 2004.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Soft Errors from Space to Ground: Historical Overview, Empirical Evidence, and Future Trends

Soft errors induced by radiation, which started as a rather exotic failure mechanism causing anomalies in satellite equipment, have become one of the most challenging issues that impact the reliability of modern electronic systems, also in ground-level applications. Many efforts have been spent in the last decades to measure, model, and mitigate radiation effects, applying numerous techniques approaching the problem at various abstraction levels. This chapter presents a historical overview of the soft-error subject and treats several “disaster stories” from the past. Furthermore, scaling trends are discussed for the most sensitive circuit types.
Tino Heijmen

Chapter 2. Single Event Effects: Mechanisms and Classification

Single Event Effects (SEEs) induced by heavy ions, protons, and neutrons become an increasing limitation of the reliability of electronic components, circuits, and systems, and have stimulated abundant past and undergoing work for improving our understanding and developing mitigation techniques. Therefore, compiling the knowledge cumulated in an abundant literature, and reporting the open issues and ongoing efforts, is a challenging task. Such a tentative should start by discussing the fundamental aspects of SEEs before reviewing the different steps that are necessary for creating comprehensive prediction models and developing efficient mitigation techniques.
Rémi Gaillard

Chapter 3. JEDEC Standards on Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray Induced Soft Errors

While the history of soft errors in commercial semiconductor devices spans over three decades, it has only been relatively recently that specifications have been created to standardize the characterization of the effects of alpha particles and neutrons on ICs. Some of the first standards developed for devices used in commercial applications come from one of the premier semiconductor industry standards body, JEDEC, formerly known as Joint Electron Device Engineering Council. The JEDEC JESD89 standards are now widely referenced in most technical publications on soft errors in commercial ICs. This chapter gives an overview of the JEDEC JESD89 series of standards, describes the technical background for their development and details the areas for future improvement.
Charles Slayman

Chapter 4. Gate Level Modeling and Simulation

This chapter presents an overview of a methodology for analyzing the behavior of combinational and sequential cells regarding “Single-Event Multiple-Transients” (SEMT) caused by nuclear reactions induced by atmospheric neutrons. The methodology uses a combination of Monte Carlo-based selection of nuclear reactions, simulation of the carriers transport in the device, and SPICE simulation. The effects of nuclear particles on the gates are monitored at the gate output by means of transient duration, amplitude, and associated occurrence probability.
Nadine Buard, Lorena Anghel

Chapter 5. Circuit and System Level Single-Event Effects Modeling and Simulation

This chapter covers the behavior of complex circuits and systems in the presence of single-event effects, and the transformation of the related faults to errors and errors to functional failures. In addition, an overview of practical methods and techniques for single-event effects analysis is presented, attempting to help the reliability engineers to cope with the single-event rate constraints of modern designs.
Dan Alexandrescu

Chapter 6. Hardware Fault Injection

Hardware fault injection is the widely accepted approach to evaluate the behavior of a circuit in the presence of faults. Thus, it plays a key role in the design of robust circuits. This chapter presents a comprehensive review of hardware fault injection techniques, including physical and logical approaches. The implementation of effective fault injection systems is also analyzed. Particular emphasis is made on the recently developed emulation-based techniques, which can provide large flexibility along with unprecedented levels of performance. These capabilities provide a way to tackle reliability evaluation of complex circuits.
Luis Entrena, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Michael Nicolaidis

Chapter 7. Integrated Circuit Qualification for Space and Ground-Level Applications: Accelerated Tests and Error-Rate Predictions

Integrated circuits (analog, digital or mixed) sensitivity evaluation to Single Event Effects (SEE) requires specific methodologies and dedicated tools. Indeed, such evaluation is based on data gathered from on-line tests performed in a suitable facility (cyclotron, linear accelerator, laser , etc.). The target circuit is exposed to particles fluxes having features (energy and range in Silicon) somewhat representative of the ones the circuit will encounter in its final environment. This chapter will describe and illustrate with experimental results, the methodologies and the hardware and software developments required for the evaluation of the sensitivity to SEE of integrated circuits. Those techniques will be applied to a SRAM-based FPGA and to a complex processor. In case of sequential circuits such as processors, the sensitivity to SEE will strongly depend on the executed program. Hardware/software fault-injection experiments, performed either on the circuit or on an available model, are proved as being complementary of radiation ground testing. Indeed, data issued from fault injection combined with data issued from radiation ground testing allow in accurately predicting the error rate of any program.
Raoul Velazco, Gilles Foucard, Paul Peronnard

Chapter 8. Circuit-Level Soft-Error Mitigation

In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern in the past for space applications, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEUs) affecting memory cells, latches, and flip-flops, and single-event transients (SETs) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this chapter, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.
Michael Nicolaidis

Chapter 9. Software-Level Soft-Error Mitigation Techniques

Several application domains exist, where the effects of Soft Errors on processor-based systems cannot be faced by acting on the hardware (either by changing the technology, or the components, or the architecture, or whatever else). In these cases, an attractive solution lies in just modifying the software: the ability to detect and possibly correct errors is obtained by introducing redundancy in the code and in the data, without modifying the underlying hardware. This chapter provides an overview of the methods resorting to this technique, outlining their characteristics and summarizing their advantages and limitations.
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Chapter 10. Specification and Verification of Soft Error Performance in Reliable Electronic Systems

This chapter describes the modeling, analysis, and verification methods used to achieve a reliability target set for transient outages in equipment used to build the backbone routing infrastructure of the Internet. We focus on ASIC design and analysis techniques that were undertaken to achieve the targeted behavior using the 65-nm technology. Considerable attention is paid to Single Event Upset in flip-flops and their potential to produce network impacting events that are not systematically detected and controlled. Using random fault injection in large-scale RTL simulations, and slack time distributions from static timing analysis, estimates of functional and temporal soft error masking effects were applied to a system soft error model to drive decisions on interventions such as the choice of flip-flops, parity protection of registers groupings, and designed responses to detected upsets. Central to the design process is a modeling framework that accounts for the upset effects and relates them to the target specification. This enables the final system to be tested using large area neutron beam radiation to confirm the specification has been met.
Allan L. Silburt, Adrian Evans, Ana Burghelea, Shi-Jie Wen, David Ward, Ron Norrish, Dean Hogle, Ian Perryman

Backmatter

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