High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

This chapter reviews recent advances in low-power design techniques for high-speed and high-effective resolution pipeline Analog-to-Digital Converters (ADCs). The advantages of replacing, in a pipeline ADC architecture, the traditional local low-resolution parallel (flash) quantizers by low-resolution successive-approximation register (SAR) ADCs are shown through a set of selected works. Some of the most promising energy-efficient residue amplification techniques are reviewed, spanning from open-loop and closed-loop amplifierless approaches to innovative and highly-scalable amplifier-based topologies.

This chapter discusses how digital assistance can be leveraged in the design of analog to digital converters. Different types of digital assistance are defined, and a few of the possible applications selected for detailed discussion. Finally, an example of an ADC implementation heavily leveraging digital assistance is presented.

An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sampling frequency is presented. The ADC fulfills all specifications for 100 Gb/s ITU-OTU4 communication over long-distance optical fiber channels. It is based on a SAR ADC, known for its superior energy efficiency and suitability for deep-submicron digital CMOS processes, as the comparator is the only true analog element. Several improvements to existing SAR ADC architectures are presented. Alternate comparators are used to increase the sampling speed at no power and area penalty, and dynamic memory is used to reduce latency in the CDAC feedback. A deep-trench capacitor-based reference buffer significantly reduces power at low output impedance, and a differential CDAC with constant common mode and fractional reference voltages optimizes comparator performance and silicon area. The 64× interleaved ADC consists of a dedicated sampling and interleaving block and 64 SAR ADCs. Four interleaved passive samplers based on a sampling switch with in-line 1:4 demultiplexer provide an initial 1:16 interleaving with high linearity and more than 20 GHz input bandwidth while using only a single supply voltage.

In this contribution, we discuss our recent advances in the automated design of continuous-time sigma-delta modulators. In the state of the art, the architectural and circuit level design of these modulators, especially if high-speed, low power or high resolution is targeted, either requires broad experience in the loop filter design, or relies on mathematical transformations which does not include the influence of non-idealities nor gives control about the signal transfer function, or the design is based on a very time consuming, massive simulation approach. Our solution is based on a detailed high level modeling, which allows to include many of the common non-idealities into the architectural design. By using an exact DT simulation of the CT modulator, and by employing a GPU-based heuristic search, a quasi real-time design optimization is obtained. The adoption of this tool, which is online available via a web page, is shown for the design of a 50 MHz, 10 bit sigma-delta modulator.

This chapter discusses the architectures of Nyquist rate Analog-to-Digital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

Analysis of recent publications reveals that high performance DAC design can be sub-divided into two types of design approaches. In essence these approaches differ as far as the control of mismatch related effects is concerned. On the one hand one can design such that these effects are intrinsically sufficiently under control but then additional advanced design techniques are required to limit the side-effects of this intrinsic approach. On the other hand one can also rely on mismatch calibration to simplify the design itself. For this approach we will also focus on a more recent specific calibration concept for high performance DACs to unify 16-bit dynamic range with GS/s data-rates. Both approaches have their strengths and weaknesses and depending on the application either one could be more favorable.

Deep sub-micron (including 20 nm and FinFET) processes have led to significant design challenges. These include process spread, I/O voltage limitations, transistor reliability, limitations in transistor W and L, restrictive physical design rules, device matching, simulation verification including parasitics, and electromigration. This chapter discusses these challenges and ways to address them, including using cascoded transistors to prevent over-voltage stress on devices, running LPE simulation verification which includes metal resistances, and using compound transistors which have DC characteristics similar to long-channel transistors.

Analog filters are widely used in several kinds of integrated mixed-signal systems, since they are intrinsically needed for in-band signal selection, out-of-band noise rejection and anti-aliasing for the A-to-D (D-to-A) conversion. CMOS technological scaling down has already entered in nm-range scenario, leading to severe degradation of some of the most important MOS device performance for analog design. Among them, lower V_DD/V_TH ratio (supply voltage and threshold voltage, respectively), higher power consumption, and transistor intrinsic gain decreasing. On the other side the increasing MOS transistor transconductance (g_m) and transition frequency (f_T) enables tens of GHz applications, which take advantage of cheaper and smart CMOS processes. Specific continuous-time analog filters will be presented in this chapter, with the aim to introduce novel circuital topologies or optimizations and techniques suitable to mitigate the severe issues present in sub-90 nm CMOS technological nodes, and at the same time to exploit the opportunity of higher technological scaling-down.

The way the electronics industry has traditionally ensured the continued reduction in cost per function year-in, year-out is to aggressively follow Moore’s Law process scaling, where the number of transistors per unit area doubles about every 2 years, coupled with a 25 % performance increase and 20 % power reduction per function with scaled V_CC. Increasingly complex process technologies are needed each chip generation to ensure continued scaling with the consequence that chip costs are going up enormously. It is also becoming more difficult to eke out performance gains each process node and to this end architectural innovation needs to go hand in hand with direct circuit porting to fully exploit the benefits of the technology. Unprecedented levels of system integration have become possible using advanced technology options, where highly complex logic, CPUs and analog processing can exist side by side in one package. FPGAs have been leading the industry in always being among the first to the node with commercial products and adopting new technologies such as 3D-IC. This chapter presents out the experience gained in following Moore’s Law and the application of “More than Moore” technology. It covers such items as process selection, 3D-IC technology, high-performance AMS features, as well as power reduction strategies and the migration steps to 20 and 16 nm CMOS.

Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this article is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65 and 32 nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. f_T and f_MAX increase though slower than in the past, r_on*C_off, a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32 nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108 GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes.

This chapter shows novel digital enhanced transmitter concepts based on RF-D/A converters as example for innovative circuit solutions mitigating the technology scaling related drawbacks for analog and RF design. Moving analog requirements from voltage to time domain allows to fully benefit from high switching speed in scaled CMOS. RFDACs are key building blocks for digital TX architectures and have to provide very high dynamic range at high clock frequencies and high power efficiency. Innovative digital RFDAC concepts are presented based on current mode and capacitive operation. Pre-distortion, calibration, distributed mixers and novel decoding schemes are employed to fulfill tough cellular and co-existence specifications and to allow multi-mode operation in future digital TX architectures.

Power management IPs become more and more attractive in deep sub-micron technologies in order to optimize the power efficiency of today’s complex chips demanding Amps of current. The development of a 28 nm analog buck DC/DC controller is presented here, showing the main design challenges and architectural choices. The main idea is to take advantage of technology scaling, so the controlling engine is purely digital, generating the discrete PWM driving signals to the off-chip power FETs. The analog circuits implement the voltage comparisons to set the output voltage level and the PWM signal buffering, which has to be realized in high voltage and with the correct timing. One of the main challenges of the analog design is presented by the requirement of a single input power supply with a wide range from 1.8 V − 5 % up to 3.3 V + 5 %, but just using 1.8 V compliant devices. Since the PWM modulator has to provide a full rail-to-rail output driving to the external FETs, an intense design phase and reliability analysis has been performed, accessing the foundry information and identifying the proper external low-gate-drive FETs. The analog layout implementation in 28 nm has to satisfy stringent rules with proper structure to guarantee that the device models match with the silicon performance, in particular for circuits where a precise signal sensing is critical. Measured results are available.

The chapter focuses on positron emission tomography (PET), a medical imaging technique that combines high speed with high complexity data processing. In PET, optical sensors detect gamma events generated by the annihilation of an electron and a positron, by measuring hundreds of individual photon times-of-arrival. These measurements are carefully analyzed, every 6.4 µs, by ultra-fast networks and distributed reconstruction algorithms, all running in parallel at several gigabit-per-second. In this context, we present an array of 4 × 4 digital silicon photomultipliers (MD-SiPMs) integrated in standard CMOS, capable of capturing and digitizing up to 32 million individual photon times-of-arrival per second, for up to 0.6 million gamma events per second. For each gamma event the equivalent energy is also computed to help the reconstruction algorithms screen out noise. The sensor is the core of the world’s first endoscopic digital PET, a tool with unprecedented levels of contrast and detail for early and accurate cancer diagnostics.

Fine-time resolution measurements are attracting increasing attention in the high-energy-physics (HEP) community, where a large number of measurement channels must often be realized with a single ASIC. In this contribution, a multi-channel time-to-digital converter (TDC) architecture with a delay-locked-loop (DLL) in its first stage and a resistive interpolation scheme in its second stage is presented. The size of the TDC’s least-significant-bit (LSB) is controlled by a reference clock and so can be continuously adjusted from 5 to 20 ps. A global calibration scheme that avoids the need to calibrate each channel separately is also used. Critical design aspects like device mismatch, supply noise sensitivity and process-voltage and temperature (PVT) variation are discussed. When realized in a 130 nm technology, the prototype ASIC achieved a single-shot resolution of better than 2.5 ps-rms. The measured integral-non-linearity (INL) and differential-non-linearity (DNL) were found to be ±1.4 LSB and ±0.9 LSB respectively.

The demand for higher integration level and lower production cost has driven mm-wave electronics, which have traditionally been implemented in III-V technologies for better RF performance, to be also implemented in CMOS. This motivates the digitization of the mm-wave systems for improved RF performance. This paper focuses on a digitally intensive architecture and time-domain circuit and calibration techniques for mm-wave frequency synthesizer. A 60-GHz all-digital phase-locked loop (ADPLL) transmitter prototype, implemented in 65-nm CMOS, achieves excellent phase noise (−75 dBc/Hz at 10 kHz offset), fast locking (3 μs), low reference spurs (−74 dBc), and linear frequency modulation up to 1 GHz in range.

Among different types of time-domain analog-to-digital-converters (ADCs), voltage-controlled-oscillator (VCO) based ADCs have gained prominence. Like other time-based ADCs, VCO based ADCs are amenable to CMOS technology scaling. They provide inherent anti-alias filtering to the input signal and achieve very high resolution by first order noise shaping the quantization error. Despite these advantages, traditional VCO based ADCs have found limited application due to poor linearity. Recently, several new techniques have been developed to improve the overall performance of such ADCs. This chapter briefly discusses such recent advances towards improving the performance of VCO based ADCs. A deterministic background calibration method to improve the linearity of VCO based ADCs is discussed in more detail.

The ever increasing demand for improved autonomy in wireless sensor devices, drives the search for new energy-efficient sensor interface topologies in CMOS technology. Recently, time-based conversion has gained a lot of interest due to its high potential to implement highly-digital circuitry. While voltage-based analog integrated circuits suffer from the decreased supply voltage and voltage swing in highly-scaled CMOS technologies, time-based processing takes advantage of the increased timing resolution. However, how do these time-based sensor interface circuits compare to their amplitude-based counterparts fundamentally? To answer this question, theoretical limits are derived in this chapter for both implementations, which shows that the sensor itself is actually the dominant factor in limiting the achievable energy efficiency. Time-based topologies, however, enable the implementation of highly-digital interfaces, which are scalable, area-efficient and have low-voltage potential. These observations are illustrated with several practical designs.

Ring amplification is a technique for performing efficient amplification in nanoscale CMOS technologies. By using a cascade of dynamically stabilized inverter stages to perform accurate amplification, ring amplifiers are able to leverage the key benefits of technology scaling, resulting in excellent efficiency and performance. A generalized view of basic small-signal theory is first presented, followed by a deeper discussion of the time-domain operation of a ringamp in the context of a specific ringamp structure. We conclude with a survey of existing ringamp implementations and techniques reported in literature.