The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor

The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain \((G_{m}R_{O})\), and unity gain cut-off frequency \((f_{T})\) are degraded with an increase in gate dielectric permittivity \((k)\). The transconductance \((G_{m})\) and gate capacitance \((C_{GG})\) are slightly affected with increase in \(k\). The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in \(k\). In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior \(G_{m}, \, C_{GG}\) and \(f_{T}\) compared to \(\hbox {SiO}_{2}\)-only and \(\hbox {HfO}_{2}\)-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to \(\hbox {SiO}_{2}\)-only and \(\hbox {HfO}_{2}\)-only DGJLT.