Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

Test Technology Technical Council Newsletter

A. Ivanov

List of Reviewers

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

S.J. Spinks, C.D. Chalk, I.M. Bell, M. Zwolinski

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

V. Stopjaková, P. Malošek, D. Mičušík, M. Matej, M. Margala

Control and Observation Structure for Analog Circuits with Current Test Data

Chun-Lung Hsu

A Graph-Based Approach to Power-Constrained SOC Test Scheduling

Chih-Pin Su, Cheng-Wen Wu

Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints

Valentin Mureşan, Xiaojun Wang, Valentina Mureşan, Mircea Vlăduţiu

A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques

D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda

Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Kanad Chakraborty

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

O. Novák, Z. Plíva, J. Nosek, A. Hlawiczka, T. Garbolino, K. Gucwa