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2019 | OriginalPaper | Buchkapitel

3. InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures

verfasst von : Sascha Roloff, Frank Hannig, Jürgen Teich

Erschienen in: Modeling and Simulation of Invasive Applications and Architectures

Verlag: Springer Singapore

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Abstract

In this chapter novel, fast, and flexible simulation techniques for modern heterogeneous NoC-based multi-core architectures are presented. They include the design and development of the full-system simulator InvadeSIM, which allows modeling complex MPSoC architectures, emulating the execution behavior of the runtime system, and simulating function and timing of invasive parallel applications apart from utilization, efficiency, and competition. A novel high-level processor simulation approach based on direct-execution and a linear timing estimation model is proposed that tackles the complexity and the heterogeneity of current multi and many-core architectures. Furthermore, a discrete-event simulation framework is presented, which allows integrating and synchronizing different simulation tasks such as software or hardware simulations. Besides processor simulation, exemplary timing models for hardware accelerators such as tightly-coupled processor arrays and special cores with instruction-set extensions are presented.

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Vorheriges Kapitel Fundamentals

Nächstes Kapitel Hybrid Network-on-Chip Simulation

Considered as realistic workloads are invasive X10 applications that dynamically request, release, and occupy computation and communication resources using InvadeX10.

Retired instructions are the actual number of instructions that have been executed for a particular program flow, i.e., without speculative executed instructions.

Causality describes the relationship between cause and consequence for a sequence of associated events. If event B is induced by event A, then, A is the cause of the consequence B and emerged temporally earlier than B. The inversion of this principle is called causality error. An example might be if the reply of a communication request arrives earlier than the request was sent.

Assuming a round-robin bus arbitration (no prioritization).

Perfect tiling is assumed.

S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate resource conflict simulation for performance analysis of multi-core systems, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Grenoble, France, 14–18 Mar 2011 (IEEE, 2011), pp. 210–215. ISBN: 978-1-61284-208-0. https://doi.org/10.1109/DATE.2011.5763044

A. Gerstlauer, Host-compiled simulation of multi-core platforms, in Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping (RSP), Fairfax, VA, USA, 8–11 June 2010 (IEEE, 2010), pp. 1–6. ISBN: 978-1-4244-7073-0. https://doi.org/10.1109/RSP.2010.5656352

S. Ha J. Teich (eds.), The Handbook of Hardware/Software Codesign (Springer, Netherlands, 2017). ISBN: 978-94-017-7266-2. https://doi.org/10.1007/978-94-017-7267-9

T. Wild, A. Herkersdorf, G.-Y. Lee, TAPES-tracebased architecture performance evaluation with system C. Design Autom. Embedded Syst. 10(2–3), 157–179, (Sept. 2005). ISBN: 0929-5585. https://doi.org/10.1007/s10617-006-9589-4CrossRef

R.E. Wunderlich et al., Statistical sampling of microarchitecture simulation. ACM Trans. Model. Comput. Simul. (TOMACS) 16(3), pp. 197–224, (July 2006). ISSN: 1049-3301. https://doi.org/10.1145/1147224.1147225CrossRef

A. Falcon, P. Faraboschi, D. Ortega, Combining simulation and virtualization through dynamic sampling, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), San Jose, CA, USA, 25–27 Apr 2007 (IEEE, 2007), pp. 72–83. ISBN: 1-4244-1081-9. https://doi.org/10.1109/ISPASS.2007.363738

F. Hannig et al., Resource-aware programming and simulation of MPSoC architectures through extension of X10, in Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany, 27–28 June 2011, (ACM, 2011), pp. 48–55. ISBN: 978-1-4503-0763-5. https://doi.org/10.1145/1988932.1988941

S. Roloff, F. Hannig, J. Teich, Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs, in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, NSW, Australia, 30 Jan–2 Feb, 2012 (IEEE, 2012), pp. 187–192. ISBN: 978-1-4673-0770-3. https://doi.org/10.1109/ASPDAC.2012.6164943

S. Roloff, F. Hannig, J. Teich, Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation, in Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES), St. Goar, Germany, 15–16 May 2012 (ACM, 2012), pp. 52–61. ISBN: 978-1-4503-1336-0. https://doi.org/10.1145/2236576.2236582

10.

C.J. Mauer, M.D. Hill, D.A. Wood, Full-system timing first simulation, in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMET RICS), Marina Del Rey, CA, USA, 15–19 June 2002 (ACM, 2002), pp. 108-116. ISBN: 1-58113-531-9. https://doi.org/10.1145/511334.511349

11.

R.C. Covington et al., The rice parallel processing Testbed, in Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Santa Fe, NM, USA, 24–27 May 1988 (ACM, 1988), pp. 4–11. ISBN: 0-89791-254-3. https://doi.org/10.1145/55595.55596

12.

S.K. Reinhardt et al., The wisconsin wind tunnel: virtual prototyping of parallel computers, in Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Santa Clara, CA, USA, 10–14 May 1993 (ACM, 1993), pp. 48–60. ISBN: 0-89791-580-1. https://doi.org/10.1145/166955.166979

13.

S.S. Mukherjee et al., Wisconsin wind tunnel II: A fast, portable parallel architecture simulator, in IEEE Concurrency 8.4 (Oct. 2000), pp. 12–20. ISSN: 1092-3063. https://doi.org/10.1109/4434.895100CrossRef

14.

G. Zheng, G. Kakulapati, L. Kalè, BigSim: a parallel simulator for performance prediction of extremely large parallel machines, in Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS), Santa Fe, NM, USA, 26–30 Apr 2004 (IEEE, 2014), pp. 78–87. ISBN: 0-7695-2132-0. https://doi.org/10.1109/IPDPS.2004.1303013

15.

T. Diop, N.E. Jerger, J. Anderson, Power modeling for heterogeneous processors, in Proceedings of the 7th Workshop on General Purpose Processing Using GPUs (GPGPU), Salt Lake City, UT, USA, 1 Mar 2014 (ACM, 2014), 90:90-90:98. ISBN: 978-1-4503-2766-4. https://doi.org/10.1145/2576779.2576790

16.

R. Bertran et al, Counter-based power modeling methods: top-down vs. bottom-up. Comput. J. 56(2), pp. 198–213 (Feb. 1, 2013). ISSN: 1460-2067. https://doi.org/10.1093/comjnl/bxs116CrossRef

17.

K. Singh, M. Bhadauria, S.A. McKee, Real time power estimation and thread scheduling via performance counters. ACM SIGARCH Comput. Archit. News 37(2), 46–55 (May 2009). ISSN: 0163-5964. https://doi.org/10.1145/1577129.1577137CrossRef

18.

G. Contreras, M. Martonosi, Power prediction for intel XScale \(\textregistered \) processors using performance monitoring unit events, in Proceedings of the International Symposium on Low Power Electronics and Design (ISPLED), San Diego, CA, USA, 8–10 Aug 2005 (ACM, 2005), pp. 221–226. ISBN: 1-59593-137-6. https://doi.org/10.1145/1077603.1077657

19.

J. Russ, M. Margaret, Run-time power estimation in high performance microprocessors, in Proceedings of the International Symposium on Low Power Electronics and Design (ISPLED), Huntington Beach, CA, USA, 6–7 Aug 2001 (ACM, 2001), pp. 135–140. ISBN: 1-58113-371-5. https://doi.org/10.1109/LPE.2001.945389

20.

S. Eranian, Perfmon2: a flexible performance monitoring interface for Linux, in Proceedings of the Ottawa Linux Symposium (OLS), Ottawa, ON, Canada. 19–22 July 2006, pp. 269–288

21.

V.M. Weaver, Linux perfevent features and overhead, in Proceedings of the 2nd International Workshop on Performance Analysis of Workload Optimized Systems (FastPath). Austin, TX, USA. 21 Apr 2013, pp. 80–86

22.

J. Henkel et al., i-Core: a run-time adaptive processor for embedded multi-core systems, in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, July 18–21, 2011, pp. 1–8

23.

J. Teich, A. Tanase, F. Hannig, Symbolic mapping of loop programs onto processor arrays. J. Signal Process. Syst. (JSPS) 77(1–2), pp. 31–59 (Oct. 2014). ISSN: 1939-8018. https://doi.org/10.1007/s11265-014-0905-0CrossRef

24.

A. Tanase et al., Symbolic multi-level loop mapping of loop programs for massively parallel processor arrays. ACM Trans. Embedded Comput. Syst. (TECS) 17(2), 31:1–31:27 (Apr. 2018). ISSN: 1539-9087. https://doi.org/10.1145/3092952CrossRef

25.

T. Austin, E. Larson, D. Ernst, SimpleScalar: an infrastructure for computer system modeling. Computer 35(2), 59–67 (Aug. 7, 2002). ISSN: 0018-9162. https://doi.org/10.1109/2.982917CrossRef

26.

M.T. Yourst, PTLsim: a cycle accurate full system x86-64 microarchitectural simulator, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS), San Jose, CA, USA, 25–27 Apr 2007 (IEEE, 2007), pp. 23–34. ISBN: 1-4244-1081-9. https://doi.org/10.1109/ISPASS.2007.363733

27.

M. Dales, SWARM 0.44 Documentation. Tech. rep. Department of Computer Science, University of Glasgow, Nov. 10, 2000. http://www.cl.cam.ac.uk/~mwd24/phd/swarm.html

28.

L. Benini et al., MPARM: exploring the multi-processor SoC design space with system C. J. VLSI Signal Process. Syst. Signal Image Video Technol. 41(2), 169–182 (Sept. 1, 2005). ISSN: 0922-5773. https://doi.org/10.1007/s11265-005-6648-1CrossRef

29.

C.J. Hughes et al., RSIM: simulating shared-memory multiprocessors with ILP processors. Computer 35(2), 40–49 (Aug. 7, 2002). ISSN: 0018-9162. https://doi.org/10.1109/2.982915CrossRef

30.

N. Binkert et al., The Gem5 simulator. ACM SIGARCH Comput. Architect. News 39(2), 1–7 (May 2011). ISSN: 0163-5964. https://doi.org/10.1145/2024716.2024718CrossRef

31.

N.L. Blinkert et al., The M5 simulator: modeling networked systems. IEEE Micro 26(4), 52–60 (Sept. 21, 2006). ISSN: 0272-1732. https://doi.org/10.1109/MM.2006.82CrossRef

32.

M.M.K. Martin et al., Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. ACM SIGARCH Comput. Archit. News 33(4), 92–99 (Nov. 2005). ISSN: 0163-5964. https://doi.org/10.1145/1105734.1105747CrossRef

33.

M.R. Hartoog et al., Generation of software tools from processor descriptions for hardware/software codesign, in Proceedings of the 34th Annual Design Automation Conference (DAC), Anaheim, CA, USA, 9–13 June 1997 (ACM, 1997), pp. 303–306. ISBN: 0-89791-920-3. https://doi.org/10.1145/266021.266110

34.

G. Hadjiyiannis, S. Hanono, S. Devadas, ISDL: an instruction set description language for retargetability, in Proceedings of the 34th Annual Design Automation Conference (DAC), Anaheim, CA, USA, 9–13 June 1997 (ACM, 1997), pp. 299–302. ISBN: 0-89791-920-3. https://doi.org/10.1145/266021.266108

35.

S. Sutarwala, P.G. Paulin, Y. Kumar, Insulin: an instruction set simulation environment, in Proceedings of the 11th International Conference on Computer Hardware Description Languages and Their Applications (CHDL), Ottawa, ON, 26–28 Apr 1993 (Canada. North-Holland Publishing Co., 1993), pp. 369–376. ISBN: 0-444-81641-0CrossRef

36.

J. Zhu, D.D. Gajski, An ultra-fast instruction set simulator, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10.3 (Dec. 10, 2002), pp. 363–373. ISSN: 1063-8210. https://doi.org/10.1109/TVLSI.2002.1043339CrossRef

37.

J. Zhu, D.D. Gajski, A Retargetable, ultra-fast instruction set simulator, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, Mar 1999 (ACM, 1999), pp. 62–69. ISBN: 1-58113-121-6. https://doi.org/10.1145/307418.307509

38.

V. Zivojnovic, S. Tjiang, H. Meyr, Compiled simulation of programmable DSP architectures. J. VLSI Signal Process. Syst. Signal Image Video Technol. 16(1), 73–80 (May 1, 1997). ISSN: 0922-5773. https://doi.org/10.1023/A:1007916402263CrossRef

39.

C. Mills, S.C. Ahalt, J. Fowler, Compiled instruction set simulation. Software Pract. Exp. 21(8), 877–889 (Aug. 1, 1991). ISSN: 1097-024X. https://doi.org/10.1002/spe.4380210807

40.

W.S. Mong, J. Zhu, DynamoSim: a trace-based dynamically compiled instruction set simulator, in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA, USA, 7–11 Nov 2004 (IEEE, 2004), pp. 131–136. https://doi.org/10.1109/ICCAD.2004.1382557

41.

M. Reshadi, P. Mishra, N. Dutt, Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, in Proceedings of the 40th Annual Design Automation Conference (DAC), Anaheim, CA, USA, June 2, 2003-June 6, 2002 (ACM, 2002), pp. 758–763. ISBN: 1-58113-688-9. https://doi.org/10.1145/775832.776026

42.

A. Nohl et al., A universal technique for fast and flexible instruction-set architecture simulation, in Proceedings of the 39th Design Automation Conference (DAC), New Orleans, LA, USA, 10–14 June 2002 (IEEE, 2002), pp. 22–27. https://doi.org/10.1109/DAC.2002.1012588

43.

R.C. Bedichek, Talisman: fast and accurate multicomputer simulation, in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Ottawa, ON, Canada, 15–19 May 1995 (ACM, 1995), pp. 14–24. ISBN: 0-89791-695-6. https://doi.org/10.1145/223587.223589

44.

P.S. Magnusson et al., Simics: a full system simulation platform. Computer 35(2), 50–58 (Aug. 7, 2002). ISSN: 0018-9162. https://doi.org/10.1109/2.982916CrossRef

45.

ARM Limited, ARM Developer Suite Debug Target Guide. Version 1.2. Sept. 1, 2017. http://infocenter.arm.com

46.

Synopsys, Inc. ARC nSIM Instruction Set Simulator for ARC Processors. Version M-2017.06. Sept. 1, 2017. https://www.synopsys.com

47.

Imperas Software Ltd. ISS—The Imperas Instruction Set Simulator. Sept. 1, 2017. http://www.imperas.com

48.

J. Larus, SPIM: A MIPS32 Simulator. Sept. 1, 2017. http://spimsimulator.sourceforge.net

49.

M. Chapman, Sulima ISA Simulator. Sept. 1, 2017. http://www.cse.unsw.edu.au

50.

M. Reshadi, N. Dutt, P. Mishra, A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. (TECS) 5(2), 431–452 (May 2006). ISSN: 1539-9087. https://doi.org/10.1145/1151074.1151083CrossRef

51.

E.C. Schnarr, M.D. Hill, J.R. Larus, Facile: a Language and Compiler for High-performance Processor Simulators, in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Snowbird, UT, USA, 20–22 June 2001 (ACM, 2001), pp. 321–331. ISBN: 1-58113-414-2. https://doi.org/10.1145/378795.378864

52.

R. Leupers, J. Elste, B. Landwehr, Generation of interpretive and compiled instruction set simulators, in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Wanchai, Hong Kong, 18–21 Jan 1999 (IEEE, 1999), pp. 339–342. ISBN: 0-7803-5012-X. https://doi.org/10.1109/ASPDAC.1999.760028

53.

A. Halambi et al., EXPRESSION: a Language for Architecture Exploration through compiler/simulator retargetability, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, 9–12 Mar 1999 (IEEE, 1999), pp. 485–490. ISBN: 0-7695-0078-1. https://doi.org/10.1109/DATE.1999.761170

54.

L.G. Murillo et al., Synchronization for hybrid MPSoC full-system simulation, in Proceedings of the 49th Annual Design Automation Conference (DAC), San Francisco, CA, USA, 3–7 June 2012 (ACM, 2012), pp. 121–126. ISBN: 978-1-4503-1199-1. https://doi.org/10.1145/2228360.2228383

55.

L. Gao et al., Multiprocessor performance estimation using hybrid simulation, in Proceedings of the 45th Annual Design Automation Conference (DAC), Anaheim, CA, USA, 8–13 June 2008 (ACM, 2008), pp. 325–330. ISBN: 978-1-60558-115-6. https://doi.org/10.1145/1391469.1391552

56.

S. Kraemer et al., HySim: a fast simulation framework for embedded software development, in Proceedings of the 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Salzburg, Austria, 30 Sept–3 Oct 2007 (IEEE, 2007), pp. 75–80. ISBN: 978-1-5959-3824-4. https://doi.org/10.1145/1289816.1289837

57.

I. Böhm, B. Franke, N. Topham, Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator, in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 19–22 July 2010 (IEEE, 2010), pp. 1–10. ISBN: 978-1-4244-7936-8. https://doi.org/10.1109/ICSAMOS.2010.5642102

58.

O. Almer et al., Scalable multi-core simulation using parallel dynamic binary translation, in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 18–21 July 2011 (IEEE, 2011), pp. 190–199. ISBN: 978-1-4577-0802-2. https://doi.org/10.1109/SAMOS.2011.6045461

59.

E.C. Schnarr, J.R. Larus, Fast out-of-order processor simulation using memoization, in Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, USA, 2–7 Oct 1998 (ACM, 1998), pp. 283-294. ISBN: 1-58113-107-0. https://doi.org/10.1145/291069.291063

60.

E. Witchel, M. Rosenblum, Embra: fast and flexible machine simulation, in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Philadelphia, PA, USA, 23–26 May 1996 (ACM, 1996), pp. 68–79. ISBN: 0-89791-793-6. https://doi.org/10.1145/233013.233025

61.

B. Cmelik, D. Keppel, Shade: a fast instruction-set simulator for execution profiling, in Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Nashville, TN, USA, 16–20 May 1994 (ACM, 1994), pp. 128–137. ISBN: 0-89791-659-X. https://doi.org/10.1145/183018.183032

62.

Imperas Software Ltd.OVP Guide to Using Processor Models. Jan. 29, 2015. http://www.imperas.com

63.

B. Barnes, J. Slice, SimNow: a fast and functionally accurate AMD x86-64 system simulator, in Tutorial at the IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, USA. Oct. 6–8, 2005

64.

M. Rosenblum et al., Complete computer system simulation: the SimOS approach.IEEE Parallel Distrib. Technol. Syst. Appl. 3(4), 34–43 (1995). ISSN: 1063-6552. https://doi.org/10.1109/88.473612CrossRef

65.

F. Bellard, QEMU, a fast and portable dynamic translator, in Proceedings of the Annual Conference on USENIX Annual Technical Conference (ATEC), Anaheim, CA, USA, 10–15 Apr 2005 (USENIX Association, 2005), p. 41

66.

Synopsys Inc. http://www.synopsys.com

67.

CoFluent Design. http://www.cofluentdesign.com

68.

Magillem Design Services. http://www.magillem.com

69.

Open Virtual Platforms, Imperas Software Ltd. http://www.ovpworld.org

70.

Z. Wang, J. Henkel, Accurate source-level simulation of embedded software with respect to compiler optimizations, in Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, Germany. EDA Consortium, 12–16 Mar 2012, pp. 382–387. ISBN: 978-3-9810801-8-6

71.

P. Razaghi, A. Gerstlauer, Automatic timing granularity adjustment for host-compiled software simulation, in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, NSW, Australia, 30 Jan–2 Feb 2012 (IEEE, 2012), pp. 567–572. ISBN: 978-1-4673-0770-3. https://doi.org/10.1109/ASPDAC.2012.6165021

72.

Z. Wang, K. Lu, A. Herkersdorf, An approach to improve accuracy of source-level TLMs of embedded software, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Grenoble, France, 14–18 Mar, 2011 (IEEE, 2011) pp. 216–221. ISBN: 978-1-61284-208-0. https://doi.org/10.1109/DATE.2011.5763045

73.

S. Stattelmann, O. Bringmann, W. Rosenstiel, Fast and accurate source-level simulation of software timing considering complex code optimizations, in Proceedings of the 48th ACM/EDAC/IEEE DesignAutomation Conference (DAC), San Diego, CA, USA, 5–10 June 2011 (ACM, 2011), pp. 486–491. ISBN: 978-1-4503-0636-2. https://doi.org/10.1145/2024724.2024838

74.

Z. Wang, A. Herkersdorf, An efficient approach for system-level timing simulation of compiler-optimized embedded software, in Proceedings of the 46th Annual Design Automation Conference (DAC), San Francisco, CA, USA, 26–31 July 2009 (ACM, 2009), pp. 220–225. ISBN: 978-1-6055-8497-3. https://doi.org/10.1145/1629911.1629973

75.

Y. Hwang, S. Abdi, D. Gajski, Cycle-approximate retargetable performance estimation at the transaction level, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, 10–14 Mar 2008 (IEEE, 2008), pp. 3–8. ISBN: 978-3-9810801-3-1. https://doi.org/10.1145/1403375.1403380

76.

J. Schnerr et al., High-performance timing simulation of embedded software, in Proceedings of the 45th Annual Design Automation Conference (DAC), Anaheim, CA, USA, 8–13 June 2008 (ACM, 2008), pp. 290–295. ISBN: 978-1-60558-115-6. https://doi.org/10.1145/1391469.1391543

Titel: InvadeSIM-A Simulation Framework for Invasive Parallel Programs and Architectures
verfasst von: Sascha Roloff
Frank Hannig
Jürgen Teich
Verlag: Springer Singapore
Buch: Modeling and Simulation of Invasive Applications and Architectures
Print ISBN: 978-981-13-8386-1

Electronic ISBN: 978-981-13-8387-8

Copyright-Jahr: 2019
DOI: https://doi.org/10.1007/978-981-13-8387-8_3

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